STRUCT PL_DMA_PCIE(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… struct pl_dma_pcie(9) β€” the PCIe port info struct, bestie

Okay so this page lives in the Kernel API Manual, and it's literally just the receipts for struct pl_dma_pcie β€” the thing that holds all the PCIe port information. It's giving "backstage pass to the Xilinx PL DMA PCIe controller" energy. Let's get into it ✨


🌸 SYNOPSIS 🌸

Here's the whole struct, exactly as it lives, no cap:

struct pl_dma_pcie {
    struct device                   *dev;
    void __iomem                    *reg_base;
    void __iomem                    *cfg_base;
    int irq;
    struct pci_config_window        *cfg;
    phys_addr_t phys_reg_base;
    struct irq_domain               *intx_domain;
    struct irq_domain               *pldma_domain;
    struct list_head                resources;
    struct xilinx_msi               msi;
    int intx_irq;
    raw_spinlock_t lock;
    const struct xilinx_pl_dma_variant   *variant;
 };

πŸŽ€ Members πŸŽ€

Time for the vibe check on every single field, one by one πŸ’–

  • dev β€” Device pointer. Your actual device, the main character.
  • reg_base β€” IO Mapped Register Base. It's the register base, but IO-mapped. πŸ¦‹
  • cfg_base β€” IO Mapped Configuration Base. Same deal but for config β€” also IO-mapped.
  • irq β€” Interrupt number. Just the number, no drama.
  • cfg β€” Holds mappings of config space window. It's the config space window's mapping holder, periodt.
  • phys_reg_base β€” Physical address of reg base. The physical one, so don't get it twisted with the IO-mapped one up there. 😭
  • intx_domain β€” Legacy IRQ domain pointer. Legacy, but still iconic.
  • pldma_domain β€” PL DMA IRQ domain pointer. The PL DMA one, obviously.
  • resources β€” Bus Resources. All the bus resources, gathered up.
  • msi β€” MSI information. Everything MSI, right here.
  • intx_irq β€” INTx error interrupt number. That's the INTx error interrupt number, specifically. πŸ”₯
  • lock β€” Lock protecting shared register access. Bestie, this one is highkey important β€” it's the lock keeping shared register access from going feral. Handle with care. πŸ’…
  • variant β€” PL DMA PCIe version check pointer. Points at the version check info so you know which PL DMA PCIe variant you're dealing with.

🌈 SEE ALSO 🌈

Go read those next, iykyk πŸ‘‘


Lowkey a reminder that all of this lives in the kernel source β€” if the code and this page ever disagree, the code ate and this page is just the flyer. πŸ™ˆ

That's the whole page, bestie β€” no crumbs left. This lil' rewrite came from ./drivers/pci/controller, dated October 2026, and it's filed under struct pl_dma_pcie(9). Slay, go forth and read the actual source ✨🫢

πŸ“¦ where this page comes from