STRUCT MSM_PINCTRL(9)

📦 version 7.3.1, in nixpkgs unstable

💖 struct msm_pinctrl(9) 💖

okay bestie, welcome to the Kernel API Manual ✨ — today's main character is struct msm_pinctrl, and she is literally the whole vibe of a pinctrl-msm device. no cap, this is the state struct, the group chat of everything that pin controller needs to remember. iykyk 🎀

🌸 NAME 🌸

struct msm_pinctrl — state for a pinctrl-msm device 🦋 (yes, that's it, that's her whole job description, and she ate)

✨ SYNOPSIS ✨

struct msm_pinctrl {
    struct device *dev;
    struct pinctrl_dev *pctrl;
    struct gpio_chip chip;
    struct pinctrl_desc desc;
    int irq;
    bool intr_target_use_scm;
    raw_spinlock_t lock;
    unsigned long dual_edge_irqs[BITS_TO_LONGS( MAX_NR_GPIO)];
    unsigned long enabled_irqs[BITS_TO_LONGS( MAX_NR_GPIO)];
    unsigned long skip_wake_irqs[BITS_TO_LONGS( MAX_NR_GPIO)];
    unsigned long disabled_for_mux[BITS_TO_LONGS( MAX_NR_GPIO)];
    unsigned long ever_gpio[BITS_TO_LONGS( MAX_NR_GPIO)];
    const struct msm_pinctrl_soc_data *soc;
    void __iomem *regs[MAX_NR_TILES];
    u32 phys_base[MAX_NR_TILES];
 };

look at all those unsigned long bitmaps bestie, it's giving organized chaos and honestly? obsessed 💅

👑 Members 👑

  • dev — device handle. the actual device she's attached to, standard issue 🫶
  • pctrl — pinctrl handle. her pinctrl half, keeping it together 😭
  • chip — gpiochip handle. the gpio side of the situation 🎀
  • desc — pin controller descriptor. literally the descriptor, no notes, slay
  • irq — parent irq for the TLMM irq_chip 🔥
  • intr_target_use_scm — when this is set, route irq to application cpu using scm calls ⭐
  • lock — Spinlock to protect register resources as well as msm_pinctrl data structures. yes she has a lock, she's not reckless 💀
  • dual_edge_irqs — Bitmap of irqs that need sw emulated dual edge detection 🔁 (done in software, because the hardware said "not my problem")
  • enabled_irqs — Bitmap of currently enabled irqs ✨
  • skip_wake_irqs — Skip IRQs that are handled by wakeup interrupt controller 🙈
  • disabled_for_mux — These IRQs were disabled because we muxed away. classic muxing betrayal 😭
  • ever_gpio — This bit is set the first time we mux a pin to gpio_func. it's a "first time" bit, lowkey sentimental 💖
  • soc — Reference to soc_data of platform specific data. platform-specific tea ☕
  • regs — Base addresses for the TLMM tiles 🧚
  • phys_base — Physical base address 🌈

🔍 SEE ALSO 🔍

a gentle reminder: the lock field exists for a reason — it protects register resources and the msm_pinctrl data structures. do not disrespect the spinlock, fr fr 🙏

that's the whole tour bestie, thanks for coming to my ted talk 💜 this page came to you from ./drivers/pinctrl/qcom, dated October 2026, and it's filed under struct msm_pinctrl(9) — periodt. 💅🎀✨

📦 where this page comes from