sifive_prci_..._dvfscorepll(9)

💖 sifive_prci_..._dvfscorepll(9) 💖

okay bestie, this page is from the Kernel API Manual and it's giving one tiny mux switch, one very specific job ✨ honestly? iconic.

🌸 NAME 🌸

sifive_prci_corepllsel_use_dvfscorepll — switch the COREPLL mux to output DVFS_COREPLL 💅

✨ SYNOPSIS ✨

void sifive_prci_corepllsel_use_dvfscorepll (struct __prci_data *pd );

🎀 ARGUMENTS 🎀

• pd — a struct __prci_data * for the PRCI containing the COREPLL mux reg. like, hand over the PRCI that has the mux reg, bestie 🫶

🦋 DESCRIPTION 🦋

So this function switches the COREPLL mux to the DVFSCOREPLL output clock, then returns once it's complete. no extra drama, no lingering — it's done and it's out ✨

💅 CONTEXT 💅

Any context is fine, fr fr. But the caller must prevent concurrent changes to the PRCI_COREPLLSEL_OFFSET register — that part is not a vibe, it's a requirement 😭

🔥 SEE ALSO 🔥

Kernel file: ./drivers/clk/sifive/sifive-prci.c

• __prci_readl(9)
• __prci_wrpll_unpack(9)
• __prci_wrpll_pack(9)
• __prci_wrpll_read_cfg0(9)
• __prci_wrpll_write_cfg0(9)
• __prci_wrpll_write_cfg1(9)
• sifive_prci_coreclksel_use_hfclk(9)
• sifive_prci_coreclksel_use_corepll(9)
• sifive_prci_coreclksel_use_final_corepll(9)
• sifive_prci_corepllsel_use_corepll(9)
• sifive_prci_hfpclkpllsel_use_hfclk(9)
• sifive_prci_hfpclkpllsel_use_hfpclkpll(9)
• __prci_register_clocks(9)
• sifive_prci_probe(9)

🫶 that's the whole page, bestie. source/version: ./drivers/clk/sifive; date: October 2026; page: sifive_prci_..._dvfscorepll(9) — slay and bye 💖