rza1_parse_gpiochip(9)

💖 NAME 💖

Okay bestie, this is rza1_parse_gpiochip(9) from the Kernel API Manual, and it is literally here to parse and register a gpio chip and pin range ✨. That’s the whole vibe: parse it, register it, slay 💅.

✨ SYNOPSIS ✨

int rza1_parse_gpiochip (struct rza1_pinctrl *rza1_pctl , struct
       fwnode_handle *fwnode , struct gpio_chip *chip , struct
       pinctrl_gpio_range *range );

🎀 ARGUMENTS 🎀

• rza1_pctl — the RZ/A1 pin controller device, aka the main character of this pin situation 👑
• fwnode — the gpio-controller firmware node, no cap 🦋
• chip — the gpio chip to register to gpiolib, periodt 💅
• range — the pin range to register to pinctrl core, iconic behavior fr fr 🌸

🌈 DESCRIPTION 🌈

So here’s the tea ☕: the gpio controller subnode shall provide a "gpio-ranges" list property — yes, shall, bestie, we are not skipping this — as defined by the gpio device tree binding documentation. That’s the rule, iykyk 💜.

🫶 SEE ALSO 🫶

The Kernel file ./drivers/pinctrl/renesas/pinctrl-rza1.c is where all this lives, and here’s the whole friend group:

• struct rza1_mux_conf(9)
• struct rza1_port(9)
• struct rza1_pinctrl(9)
• rza1_pin_reset(9)
• rza1_pin_set_direction(9)
• rza1_pin_mux_single(9)
• rza1_gpio_request(9)
• rza1_gpio_free(9)
• rza1_gpio_get(9)
• rza1_dt_node_pin_count(9)
• rza1_parse_pinmux_node(9)
• rza1_dt_node_to_map(9)
• rza1_set_mux(9)
• rza1_gpio_register(9)
• rza1_pinctrl_register(9)

Mwah 💋 — this little love letter comes from ./drivers/pinctrl/renesas and it’s dated October 2026. Bye bestie, go register those pins responsibly 🫶🎀