riscv_set_icache_flush_ctx(9)

💅 riscv_set_icache_flush_ctx(9) — the Kernel API Manual page, bestie edition 🎀

okay so this is a page straight out of the Kernel API Manual and it's literally all about whether your userspace is allowed to yeet fence.i instructions around 💖

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✨ NAME ✨

riscv_set_icache_flush_ctx — turn icache flushing instructions on or off in userspace, no cap 🫶

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🌸 SYNOPSIS 🌸

int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long scope);

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🦋 ARGUMENTS 🦋

• ctx — this one sets the type of icache flushing instructions that are permitted or prohibited in userspace. the supported values are described down below, keep scrolling 💅
• scope — and this sets the scope of where those icache flushing instructions are allowed to be emitted. supported values also below, i gotchu ⭐

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👑 DESCRIPTION 👑

🍓 supported values for ctx:

• PR_RISCV_CTX_SW_FENCEI_ON — allows fence.i in user space ✨
• PR_RISCV_CTX_SW_FENCEI_OFF — disallows fence.i in user space. every thread in a process gets affected when scope == PR_RISCV_SCOPE_PER_PROCESS, so like… caution, bestie 😭 use this flag only when you can guarantee that no thread in the process will emit fence.i from this point onward. no take-backs, fr fr.

🧚 supported values for scope:

• PR_RISCV_SCOPE_PER_PROCESS — makes sure the icache of any thread in this process is coherent with instruction storage upon migration 👑
• PR_RISCV_SCOPE_PER_THREAD — makes sure the icache of the current thread is coherent with instruction storage upon migration 🦋

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so when scope == PR_RISCV_SCOPE_PER_PROCESS, all threads in the process are permitted to emit icache flushing instructions. whenever any thread in the process gets migrated, the corresponding hart's icache will be guaranteed to be consistent with instruction storage 🔥

but — and this is the important part — it does not enforce any guarantees outside of migration. if a thread modifies an instruction that another thread may attempt to execute, that other thread must still emit an icache flushing instruction before attempting to execute the potentially modified instruction. and yes, this has to be performed by the user-space program itself 💀

in per-thread context (eg. scope == PR_RISCV_SCOPE_PER_THREAD) only the thread calling this function is permitted to emit icache flushing instructions. when the thread is migrated, the corresponding hart's icache will be guaranteed to be consistent with instruction storage 🌈

on kernels configured without SMP, this function is a nop — because migrations across harts will not occur. literally does nothing, iconic 🙈

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💜 SEE ALSO 💜

• Kernel file ./arch/riscv/mm/cacheflush.c — go read it, iykwim ✨

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and that's the whole page, bestie 🫶 this one lives in ./arch/riscv/mm, dated October 2026, and its official little name tag is riscv_set_icache_flush_ctx(9) — slay 💅🎀