pp_od_clk_voltage(9)

📦 version 7.3.1, in nixpkgs unstable

💖 pp_od_clk_voltage 💖

okay so this is a page straight out of the Kernel API Manual, and it's literally about the amdgpu driver's sysfs API for tweaking the clocks and the voltages in every single power level inside a power state. pp_od_clk_voltage is the file that does all of that. bestie, it's giving "I control the power state now" energy 👑

one thing before you touch anything: what's exposed here is the actual memory controller clock rate, not the effective memory clock of the DRAMs. so if you want the pretty number, you gotta do math. the formula is right here, don't worry 🫶

🧮 Clock conversion (Mhz)

  • HBM: effective_memory_clock = memory_controller_clock * 1
  • G5: effective_memory_clock = memory_controller_clock * 1
  • G6: effective_memory_clock = memory_controller_clock * 2

🔥 DRAM data rate (MT/s)

  • HBM: effective_memory_clock * 2 = data_rate
  • G5: effective_memory_clock * 4 = data_rate
  • G6: effective_memory_clock * 8 = data_rate

🌈 Bandwidth (MB/s)

  • data_rate * vram_bit_width / 8 = memory_bandwidth

🍓 Some examples

G5 on RX460:

memory_controller_clock = 1750 Mhz
effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
data rate = 1750 * 4 = 7000 MT/s
memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s

G6 on RX5700:

memory_controller_clock = 875 Mhz
effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
data rate = 1750 * 8 = 14000 MT/s
memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s

🧚 < For Vega10 and previous ASICs >

Reading the file will display:

  • a list of engine clock levels and voltages labeled OD_SCLK
  • a list of memory clock levels and voltages labeled OD_MCLK
  • a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE

To manually adjust these settings, first select manual using power_dpm_force_performance_level. Enter a new value for each level by writing a string that contains "s/m level clock voltage" to the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 810 mV. When you have edited all of the states as needed, write "c" (commit) to the file to commit your changes. If you want to reset to the default power levels, write "r" (reset) to the file to reset them.

🦋 < For Vega20 and newer ASICs >

Reading the file will display:

  • minimum and maximum engine clock labeled OD_SCLK
  • minimum(not available for Vega20 and Navi1x) and maximum memory clock labeled OD_MCLK
  • minimum and maximum fabric clock labeled OD_FCLK (SMU13)
  • three <frequency, voltage> points labeled OD_VDDC_CURVE. They can be used to calibrate the sclk voltage curve. This is available for Vega20 and NV1X.
  • voltage offset(in mV) applied on target voltage calculation. This is available for Sienna Cichlid, Navy Flounder, Dimgrey Cavefish and some later SMU13 ASICs. For these ASICs, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset"
  • a list of valid ranges for sclk, mclk, voltage curve points or voltage offset labeled OD_RANGE

🌸 < For APUs >

Reading the file will display:

  • minimum and maximum engine clock labeled OD_SCLK
  • a list of valid ranges for sclk labeled OD_RANGE

🎀 < For VanGogh >

Reading the file will display:

  • minimum and maximum engine clock labeled OD_SCLK
  • minimum and maximum core clocks labeled OD_CCLK
  • a list of valid ranges for sclk and cclk labeled OD_RANGE

💅 To manually adjust these settings

  • First select manual using power_dpm_force_performance_level
  • For clock frequency setting, enter a new value by writing a string that contains "s/m/f index clock" to the file. The index should be 0 if to set minimum clock. And 1 if to set maximum clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. "m 1 800" will update maximum mclk to be 800Mhz. "f 1 1600" will update maximum fabric clock to be 1600Mhz. For core clocks on VanGogh, the string contains "p core index clock". E.g., "p 2 0 800" would set the minimum core clock on core 2 to 800Mhz.

For sclk voltage curve supported by Vega20 and NV1X, enter the new values by writing a string that contains "vc point clock voltage" to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update point1 with clock set as 300Mhz and voltage as 600mV. "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and voltage 1000mV.

For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey Cavefish and some later SMU13 ASICs, enter the new value by writing a string that contains "vo offset". E.g., "vo -10" will update the extra voltage offset applied to the whole v/f curve line as -10mv.

  • When you have edited all of the states as needed, write "c" (commit) to the file to commit your changes
  • If you want to reset to the default power levels, write "r" (reset) to the file to reset them
💀 fr fr do not skip that manual-mode step first, and do not forget the commit — editing without committing is lowkey just vibes and nothing happens.

✨ SEE ALSO ✨

and that's the whole page, bestie — it lives at ./drivers/gpu/drm/amd/pm, dated October 2026, and it's literally titled pp_od_clk_voltage(9). go forth and overdrive responsibly 🫶✨

📦 where this page comes from