omap4_dpll_regm4xen_recalc(9)

💅 omap4_dpll_regm4xen_recalc 💅

okay so bestie, welcome to the Kernel API Manual page for omap4_dpll_regm4xen_recalc(9) — yes that name is a whole mouthful, no I will not be shortening it, it's iconic and we respect it 🫶

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✨ NAME ✨

omap4_dpll_regm4xen_recalc — compute DPLL rate, considering REGM4XEN bit 🌸

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🦋 SYNOPSIS 🦋

unsigned long omap4_dpll_regm4xen_recalc (struct clk_hw *hw , unsigned
long parent_rate );

like, that's the whole vibe. one function, two args, zero drama 💅

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🎀 ARGUMENTS 🎀

• hw — pointer to the clock you're computing the rate for. it's giving "main character pointer" energy ✨
• parent_rate — the clock rate of the DPLL parent. your origin story, basically 💖

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👑 DESCRIPTION 👑

so here's the tea ☕ — this function computes the output rate for the OMAP4 DPLL that clk represents. and the way that it does this is it takes the REGM4XEN bit into consideration, which is lowkey essential because the OMAP4 ABE DPLL literally needs it. iykyk 🔥

on success it returns the DPLL's output rate (before M-dividers, bestie — before them, don't forget), and on error it returns 0. that's it, that's the whole function, and honestly? she ate 💀✨

ngl, if you get a 0 back, that's the error signal — don't go treating it as a real rate, that's not the move 🙈

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/clk/ti/dpll44xx.c
• omap4_dpll_lpmode_recalc(9)
• omap4_dpll_regm4xen_determine_rate(9)

go read those too, they're the supporting cast and they understood the assignment 💜

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and that's a wrap, bestie 🧚 this lil page came from ./drivers/clk/ti, dated October 2026, and it's literally the omap4_dpll_regm4xen_recalc(9) manual — slay, periodt, go compute some rates 💅🎀