omap2_get_dpll_rate(9)

✨ NAME ✨

omap2_get_dpll_rate — returns the current DPLL CLKOUT rate 💖 and yes bestie, this is from the Kernel API Manual, page omap2_get_dpll_rate(9).

🛠️ SYNOPSIS 🛠️

here’s the exact signature, no cap:

unsigned long omap2_get_dpll_rate (struct clk_hw_omap *clk );

🌸 ARGUMENTS 🌸

• clk — the struct clk * of a DPLL. that’s the whole vibe 🫶

🦋 DESCRIPTION 🦋

okay so DPLLs can be locked or bypassed — basically enabled or disabled, periodt. when a DPLL is locked, its output depends on the M and N values. when it’s bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock or sys_clk. ✨

bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and 2 are bypassed with dpll1_fclk and dpll2_fclk respectively (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. fr fr, that’s the breakdown 💅

it returns the current DPLL CLKOUT rate (not CLKOUTX2) if the DPLL is locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 if the clock clk is not a DPLL. lowkey important, highkey iconic 🎀

🔥 SEE ALSO 🔥

• Kernel file ./drivers/clk/ti/clkt_dpll.c
• _omap2_dpll_is_in_bypass(9)
• omap2_dpll_determine_rate(9)

that’s the whole page, bestie! sourced from ./drivers/clk/ti, dated October 2026, and filed under omap2_get_dpll_rate(9) — go off, kernel queen 👑💜