mipi_dsi_du...te_seq_multi(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

✨ mipi_dsi_dual_generic_write_seq_multi(9) ✨

okay so bestie, welcome to the Kernel API Manual πŸ’– and honestly? this page is a little baddie. we're talking mipi_dsi_dual_generic_write_seq_multi β€” literally the macro that hits up both DSI interfaces with a generic write packet, one after the other. no cap. πŸŽ€


🌸 NAME 🌸

mipi_dsi_dual_generic_write_seq_multi β€” transmit data using a generic write packet to two dsi interfaces, one after the other πŸ¦‹


πŸ’… SYNOPSIS πŸ’…

mipi_dsi_dual_generic_write_seq_multi (_ctx , _dsi1 , _dsi2 , _seq... );

πŸŽ€ ARGUMENTS πŸŽ€

  • _ctx β€” the context for multiple DSI transactions. it's giving "keep track of everything for me" energy 🫢
  • _dsi1 β€” the first DSI interface, aka the first one to receive the packet πŸ‘‘
  • _dsi2 β€” the second DSI interface, the other recipient of the packet πŸ’œ
  • _seq β€” the buffer containing the payload, like the actual stuff we're sending πŸ“¦

πŸ”₯ DESCRIPTION πŸ”₯

so here's the tea β˜• β€” this macro sends the specified generic packet twice, once per each of the two interfaces you supply. and why do we care? because it's super useful for reducing duplication of code in panel drivers which use two parallel serial interfaces. the way that saves you from copy-pasting the same nonsense... obsessed. πŸ’–

⚠️ big warning bestie: if an error occurs while transmitting the packet to the first DSI interface, the packet will not be sent to the second DSI interface. so like, first one has to slay or the second one doesn't even get a turn 😭

and the best part? this macro will print errors for you πŸ‘ and error handling is optimized for callers that call this multiple times in a row. literally built different. periodt. πŸ’…


🌈 SEE ALSO 🌈


and that's the whole vibe check, bestie 🧚 source is ./include/drm, dated October 2026 β€” go forth and write your dual-DSI packets, ily, mwah πŸ’‹πŸ’–πŸŒŸ

πŸ“¦ where this page comes from