mdp5_ctl_commit(9)

✨ NAME ✨

mdp5_ctl_commit — Register Flush 💅

okay so this is the Kernel API Manual page for mdp5_ctl_commit(9), bestie, and it's literally all about telling the display controller "hey girl, these registers are done being written, you can go ahead and swap in the new copy" 🎀

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🌸 SYNOPSIS 🌸

u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
                    u32 flush_mask, bool start);

that's the whole vibe. it takes four things and hands you back a u32. slay ✨

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🦋 ARGUMENTS 🦋

• ctl — the CTL instance 🫶 like, the actual control object you're working with, no cap.
• pipeline — the encoder's INTF + MIXER configuration 🌈 it's giving "here's how this display pipeline is set up."
• flush_mask — bitmask of display controller hw blocks to flush 💀 every bit is a hardware block that needs its flush.
• start — if true, immediately update flush registers and set the START bit 🔥 otherwise accumulate flush_mask bits until we are ready to START. so it's either "go now" or "hold that thought, we're collecting."

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💖 DESCRIPTION 💖

The flush register is used to indicate several registers are all programmed, and are safe to update to the back copy of the double buffered registers ✨ think of it as the group chat read receipt for your register writes — "yes bestie, we're all done here, you can flip to the new version."

Some registers' FLUSH bits are shared when the hardware does not have dedicated bits for them 😭 tragic, I know. handling these is the job of fix_sw_flush 👑 so that function is the one doing the messy cleanup, not this one.

CTL registers need to be flushed in some circumstances; if that is the case, some trigger bits will be present in both the flush mask and ctl->pending_ctl_trigger 🌀

fr fr, pay attention to that overlap — same bits showing up in two places is intentional, not a bug 💅

Return H/W flushed bit mask. ⭐ that's the return value, a u32 with the hardware-flushed bits in it.

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🔥 SEE ALSO 🔥

• Kernel file ./drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 👀 go read the source, iykyk
• mdp5_ctl_set_encoder_state(9) 🌸 the sibling function, iconic in its own right

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and that's the whole page, bestie 🫶 it comes to you from ./drivers/gpu/drm/msm/disp/mdp5 💜 and it's dated October 2026 🎀 — mwah, go flush those registers responsibly ✨💅