iosapic_load_irt(9)

🌸 NAME 🌸

okay so bestie, welcome to iosapic_load_irt(9) from the Kernel API Manual — this is the one that fills in the interrupt routing table, and it's giving very “I know my way around a SAPIC” energy. 💅

• iosapic_load_irt — Fill in the interrupt routing table.

✨ SYNOPSIS ✨

int iosapic_load_irt (unsigned long cell_num , struct irt_entry **irt );

🎀 ARGUMENTS 🎀

• cell_num — the cell number of the CPU we're currently executing on.
• irt — the address to place the new IRT at; return The number of entries found.

🦋 DESCRIPTION 🦋

okay so the "Get PCI INT Routing Table Size" option returns the number of entries in the PCI interrupt routing table for the cell specified in the cell_number argument. The cell number must be for a cell within the caller's protection domain. No cap, that part is non-negotiable. 🔥

The "Get PCI INT Routing Table" option returns, for the cell specified in the cell_number argument, the PCI interrupt routing table in the caller allocated memory pointed to by mem_addr. We assume the IRT only contains entries for I/O SAPIC and calculate the size based on the size of I/O sapic entries. That's the whole assumption, bestie. 💖

The PCI interrupt routing table entry format is derived from the IA64 SAL Specification 2.4. The PCI interrupt routing table defines the routing of PCI interrupt signals between the PCI device output "pins" and the IO SAPICs' input "lines" (including core I/O PCI devices). This table does NOT include information for devices/slots behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec. for the architected method of routing of IRQ's behind PPB's.

🔥 SEE ALSO 🔥

• Kernel file ./drivers/parisc/iosapic.c

and that's the whole vibe, bestie: ./drivers/parisc source/version, dated October 2026, signing off on iosapic_load_irt(9) — slay, periodt. 🫶💅