ioremap_uc(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

okay bestie, welcome to ioremap_uc(9) from the Kernel API Manual β€” this is the one that maps bus memory into CPU space as strongly uncachable, no cap πŸ’…βœ¨

πŸ’– NAME πŸ’–

ioremap_uc β€” map bus memory into CPU space as strongly uncachable. That’s the whole vibe, and it ate.

✨ SYNOPSIS ✨

void __iomem * ioremap_uc (resource_size_t phys_addr , unsigned long
size );

πŸŽ€ ARGUMENTS πŸŽ€

  • phys_addr β€” bus address of the memory. Yes bestie, the bus address.
  • size β€” size of the resource to map. The amount you’re mapping, periodt.

πŸ¦‹ DESCRIPTION πŸ¦‹

Okay so ioremap_uc performs a platform specific sequence of operations to make bus memory CPU accessible via the readb/readw/readl/writeb/writew/writel functions and the other mmio helpers. The returned address is not guaranteed to be usable directly as a virtual address. That’s a real caveat β€” don’t just assume it’s a normal virtual address, bestie 😭

This version of ioremap ensures that the memory is marked with a strong preference as completely uncachable on the CPU when possible. For non-PAT systems this ends up setting page-attribute flags PCD=1, PWT=1. For PAT systems this will set the PAT entry for the pages as strong UC. This call will honor existing caching rules from things like the PCI bus. Note that there are other caches and buffers on many busses. In particular driver authors should read up on PCI writes. Like, actually read up β€” this is important driver-author lore πŸ‘‘

It’s useful if some control registers are in such an area and write combining or read caching is not desirable:

Must be freed with iounmap. 🫢 Don’t forget, or the vibe check will not pass.

🌈 SEE ALSO 🌈

Kernel file ./arch/x86/mm/ioremap.c β€” plus these bestie references: ioremap(9), ioremap_wc(9), ioremap_wt(9), iounmap(9). Go read them, iykyk πŸ’œ


mwah πŸ’– β€” this page comes from ./arch/x86/mm, dated October 2026, for ioremap_uc(9). Bye bestie! βœ¨πŸŽ€

πŸ“¦ where this page comes from