intel_set_memory_cxsr(9)

🎀 NAME 🎀

okay so bestie, welcome to intel_set_memory_cxsr(9) from the Kernel API Manual—this page is literally about configuring CxSR state, and yes it’s giving low-level display energy. 💅

• intel_set_memory_cxsr — Configure CxSR state ✨

✨ SYNOPSIS ✨

the signature, untouched because we respect the code:

bool intel_set_memory_cxsr (struct intel_display *display , bool enable );

🧾 ARGUMENTS 🧾

• display — display device. the whole display device vibe 🫶
• enable — Allow vs. disallow CxSR. yes, it’s the yes/no switch, bestie 🎚️

💫 DESCRIPTION 💫

Okay so what this actually does: it allows or disallows the system to enter a special CxSR (C-state self refresh) state. 🫶

What typically happens in CxSR mode is that several display FIFOs may get combined into a single larger FIFO for a particular plane—this is the so-called max FIFO mode—so the system can defer memory fetches longer, and the memory will enter self refresh. Iconic behavior, honestly. ✨

heads up #1: enabling CxSR does not guarantee that the system will enter this special mode, and it also does not guarantee that the system stays in that mode once entered. So this just allows/disallows the system to autonomously utilize CxSR mode. Other factors such as core C-states will affect when/if the system actually enters/exits CxSR mode. no cap 💀

heads up #2: on VLV/CHV this actually only controls the max FIFO mode, and the system is free to enter/exit memory self refresh at any time even when the use of CxSR has been disallowed. plot twist 🙈

While the system is actually in the CxSR/max FIFO mode, some plane control registers will not get latched on vblank. Thus, in order to guarantee the system will respond to changes in the plane registers, we must always disallow CxSR prior to making changes to those registers. Unfortunately, the system will re-evaluate the CxSR conditions at frame start, which happens after vblank start (which is when the plane registers would get latched), so we can’t proceed with the plane update during the same frame where we disallowed CxSR. it’s giving timing drama and you just have to respect it 😭

Certain platforms also have a deeper HPLL SR mode. Fortunately, the HPLL SR mode depends on CxSR itself, so we don’t have to hand hold the hardware w.r.t. HPLL SR when writing to plane registers. Disallowing just CxSR is sufficient. slay 💅

🔮 SEE ALSO 🔮

• Kernel file ./drivers/gpu/drm/i915/display/i9xx_wm.c
• intel_wm_method1(9), intel_wm_method2(9), intel_calculate_wm(9)

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and that’s the whole page, bestie 🎀 this cutie lives at ./drivers/gpu/drm/i915/display, dated October 2026, and it’s filed under intel_set_memory_cxsr(9). mwah 💖