gen9_set_dc_state(9)

✨ gen9_set_dc_state(9) ✨

okay bestie, so this is a page straight out of the Kernel API Manual — it's gen9_set_dc_state(9) and it's literally all about telling the display power hardware what to do. sit down, grab a strawberry 🍓, we're getting into it.

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🌸 NAME 🌸

gen9_set_dc_state — set target display C power state 💅

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🦋 SYNOPSIS 🦋

void gen9_set_dc_state (struct intel_display *display , u32 state );

that's the whole vibe. two args, zero drama, one very important power state.

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🎀 ARGUMENTS 🎀

• display — the display instance in question, aka which display we're talking to 🫶
• state — the target DC power state you want, and ngl it's one of these bad boys:
  • DC_STATE_DISABLE
  • DC_STATE_EN_UPTO_DC5
  • DC_STATE_EN_UPTO_DC6
  • DC_STATE_EN_DC9

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👑 DESCRIPTION 👑

so what this function actually does is signal to the DMC firmware/HW the target DC power state that got passed in through state 🔥

and here's the slay part: the DMC/HW can turn off individual display clocks and power rails when it's entering a deeper DC power state (deeper = higher in number, iykyk), and it turns those same things back on when it's exiting that state and heading to a shallower power state (shallower = lower in number). the HW is the main character here — it decides when to actually enter a given state, on an on-demand basis, for instance depending on the active state of display pipes. and the state of display registers that are backed by affected power rails gets saved/restored as needed. no cap. 💖

based on all that, here's the tea you need to internalise: enabling a deeper DC power state is asynchronous wrt. enabling it. but disabling a deeper power state is synchronous — for instance, setting DC_STATE_DISABLE won't complete until all HW resources are turned back on and register state is restored. and this is guaranteed by the MMIO write to DC_STATE_EN blocking until the state is restored. periodt. 💅

honestly this is the part to remember for the exam: deeper state going in = async, deeper state coming out = sync, and that blocking MMIO write is the whole reason why. iconic behaviour tbh ✨

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/gpu/drm/i915/display/intel_display_power_well.c — go read it, bestie, it's giving source-of-truth 🦋

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okay that's the page!! 💜 this absolute gem comes to you from the source path ./drivers/gpu/drm/i915/display and it's dated October 2026, and the manual page goes by gen9_set_dc_state(9) — mwah, go forth and set those power states responsibly 🎀✨