FIFO UNDERRUN HANDLING(9)

🎀 fifo underrun handling 🎀

Kernel API Manual check — bestie, this is the fifo underrun handling(9) page, and it’s actually such a useful little corner of the kernel. ✨

Okay so the i915 driver checks for display fifo underruns using the interrupt signals provided by the hardware. This is enabled by default and is fairly useful to debug display issues, especially watermark settings. genuinely iconic debugging behavior 💅

If an underrun is detected, this is logged into dmesg. To avoid flooding logs and occupying the cpu, underrun interrupts are disabled after the first occurrence until the next modeset on a given pipe. periodt — no log spam, no cpu hogging.

Heads up, bestie: underrun detection on gmch platforms is a bit more ugly since there is no interrupt (despite that the signalling bit is in the PIPESTAT pipe interrupt register). 😭

Also, on some other platforms underrun interrupts are shared, which means that if we detect an underrun we need to disable underrun reporting on all pipes. it’s giving “one alarm, whole floor evacuates” energy.

The code also supports underrun detection on the PCH transcoder. slay. 🌸

👀 SEE ALSO 👀

• Kernel file: ./drivers/gpu/drm/i915/display/intel_fifo_underrun.c
• intel_set_cpu_fifo_underrun_reporting(9)
• intel_set_pch_fifo_underrun_reporting(9)
• intel_cpu_fifo_underrun_irq_handler(9)
• intel_pch_fifo_underrun_irq_handler(9)
• intel_check_cpu_fifo_underruns(9)
• intel_check_pch_fifo_underruns(9)

Source/version: ./drivers/gpu/drm/i915/display · Date: October 2026 — okay that’s the whole fifo underrun handling(9) moment, ily, bye bestie 💖🫶✨