dcn42_hw_block_power_up(9)

📦 version 7.3.1, in nixpkgs unstable

💅 dcn42_hw_block_power_up(9) — from the Kernel API Manual, bestie

okay so picture this: you're in the kernel API manual, this is dcn42_hw_block_power_up(9), and it's literally the glow-up ritual for a hardware block ✨

🌸 NAME 🌸

dcn42_hw_block_power_up — the power up sequence, aka the "wake up babe, we're going in" moment 💖

🎀 SYNOPSIS 🎀

void dcn42_hw_block_power_up (struct dc *dc , struct pg_block_update
*update_state );

🦋 ARGUMENTS 🦋

  • dc — the current DC state. like, the whole vibe of the display core rn 🫶
  • update_state — the update PG sequence states for the HW block. it's giving "keep the receipts" 💅

✨ DESCRIPTION ✨

so the description lays out the following sequence for the ON-OFF (ONO) on power up. there are a lot of regions and ngl every single one of them is here, no skipping 👑

  • ONO Region 0, DCPG 22: dccg dcio dcoh
  • ONO Region 1, DCPG 26: dio
  • ONO Region 3, DCPG 24: mpc, opp, optc, dwb
  • ONO Region 6, DCPG 16: dsc0
  • ONO Region 8, DCPG 17: dsc1
  • ONO Region 10, DCPG 18: dsc2
  • ONO Region 12, DCPG 19: dsc3
  • ONO Region 2, DCPG 23: dchubbub, dchububmem, dchvm
  • ONO Region 5, DCPG 0: dchubp0, dpp0
  • ONO Region 7, DCPG 1: dchubp1, dpp1
  • ONO Region 9, DCPG 2: dchubp2, dpp2
  • ONO Region 11, DCPG 3: dchubp3, dpp3
  • ONO Region 4, DCPG 25: hpo
🚨 real talk though, bestie: No sequential power up/down ordering for DCN42. periodt. don't invent an order that isn't there 😭

🔥 SEE ALSO 🔥

  • Kernel file ./drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
  • dcn42_hw_block_power_down(9) — the flip side, the "ok bye" energy 🌈

okay and the little sign-off at the bottom: this page lives at ./drivers/gpu/drm/amd/display/... and it's dated October 2026 🎀 that's the whole manual page, mwah, no cap 💜⭐

📦 where this page comes from