dcn35_hw_block_power_up(9)

💖 NAME 💖

dcn35_hw_block_power_up — the power up sequence, bestie. that's it, that's the whole vibe ✨

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🦋 SYNOPSIS 🦋

void dcn35_hw_block_power_up (struct dc *dc , struct pg_block_update
*update_state );

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🎀 ARGUMENTS 🎀

• dc — the Current DC state, like the main character of the whole operation 👑
• update_state — updates the PG sequence states for the HW block, no cap 🫶

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🌈 DESCRIPTION 🌈

okay so here's the tea, this is the sequence that describes the ON-OFF (ONO) for power up 💅 lowkey iconic:

• ONO Region 0, DCPG 22: dccg dio dcio — SKIPPED
• ONO Region 2, DCPG 24: mpc opp optc dwb
• ONO Region 5, DCPG 16: dsc0
• ONO Region 7, DCPG 17: dsc1
• ONO Region 9, DCPG 18: dsc2
• ONO Region 11, DCPG 19: dsc3
• ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem — SKIPPED. PMFW will power up at IPS2 exit 🔥
• ONO Region 4, DCPG 0: dchubp0, dpp0
• ONO Region 6, DCPG 1: dchubp1, dpp1
• ONO Region 8, DCPG 2: dchubp2, dpp2
• ONO Region 10, DCPG 3: dchubp3, dpp3
• ONO Region 3, DCPG 25: hpo — SKIPPED

ngl, notice the order is doing its own little dance fr fr — it's not just 0 through 11 in a row, so don't come for me 💀

and if sequential ONO is specified? the order gets modified from ONO Region 0 -> ONO Region 11 ascending, periodt ✨

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🧚 SEE ALSO 🧚

• Kernel file ./drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c — the source, go read it iykyk 📖
• dcn35_hw_block_power_down(9) — the reverse girlypop, the power down version 🫶

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okay that's the whole page bestie, you ate that 💅 this was dcn35_hw_block_power_up(9) from the Kernel API Manual, kernel file ./drivers/gpu/drm/amd/display/..., dated October 2026 — mwah, love u, go power up some blocks 🌸⭐💜