dcn351_hw_block_power_up(9)

💅 dcn351_hw_block_power_up (9) — Kernel API Manual

okay so bestie, sit down, because we're talking about dcn351_hw_block_power_up — it's a kernel API manual page, and it's literally the power-up sequence. no cap, this is the glow-up routine for HW blocks ✨

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🌸 NAME 🌸

dcn351_hw_block_power_up — power up sequence 💖

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🎀 SYNOPSIS 🎀

void dcn351_hw_block_power_up (struct dc *dc , struct pg_block_update
*update_state );

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🦋 ARGUMENTS 🦋

• dc — Current DC state 🫶
• update_state — update PG sequence states for HW block ✨

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👑 DESCRIPTION 👑

The following sequence describes the ON-OFF (ONO) for power up:

• ONO Region 0, DCPG 22: dccg dio dcio — SKIPPED 🙈
• ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem — SKIPPED. PMFW will power up at IPS2 exit 💀
• ONO Region 2, DCPG 24: mpc opp optc dwb 🔥
• ONO Region 3, DCPG 25: hpo — SKIPPED 🙈
• ONO Region 4, DCPG 0: dchubp0, dpp0 ✨
• ONO Region 5, DCPG 16: dsc0 ✨
• ONO Region 6, DCPG 1: dchubp1, dpp1 ✨
• ONO Region 7, DCPG 17: dsc1 ✨
• ONO Region 8, DCPG 2: dchubp2, dpp2 ✨
• ONO Region 9, DCPG 18: dsc2 ✨
• ONO Region 10, DCPG 3: dchubp3, dpp3 ✨
• ONO Region 11, DCPG 19: dsc3 ✨

bestie note 🫶: regions 0, 1 and 3 are the ones that are SKIPPED — don't come for me, that's just what the sequence says. Region 1's skip is because PMFW will power up at IPS2 exit. iykyk 💅

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_hwseq.c
• dcn351_hw_block_power_down(9)

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and that's the whole page, periodt 💜 shoutout to ./drivers/gpu/drm/amd/display/... for the source/version vibes and to October 2026 for the date — iconic, no notes 🎀🦋💖