cxl_pci_get_latency(9)

💅 cxl_pci_get_latency(9)

okay so bestie, welcome to the Kernel API Manual — this one's a lil function from the kernel called cxl_pci_get_latency, and honestly? it's giving "quiet math queen." she just crunches numbers about your PCIe link and hands you back a latency. no drama. 🎀

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✨ NAME ✨

cxl_pci_get_latency — calculate the link latency for the PCIe link

like literally, that's the whole job. she computes the link latency. that's it. that's her. 🦋

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🌸 SYNOPSIS 🌸

long cxl_pci_get_latency (struct pci_dev *pdev );

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🫶 ARGUMENTS 🫶

• pdev — the PCI device. that's your girl. you hand her a PCI device and she does the math on it. 💖

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⭐ RETURN ⭐

she returns the calculated latency, or 0 for no latency. no latency, no problem, no cap. ✨

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🔥 DESCRIPTION 🔥

okay so this is all straight out of the CXL Memory Device SW Guide v1.0 2.11.4 — §Link latency calculation, main character energy. the formula is:

Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency

now let's break it down, because some of these terms are lowkey doing nothing:

• LinkProgationLatency is negligible, so 0 will be used. (yes — it's spelled that way in the source, i'm not fixing it, that's her name 💀)
• RetimerLatency is assumed to be negligible and 0 will be used. so both of those? zeros. gone. not invited to the party. 🙈
• FlitLatency = FlitSize / LinkBandwidth — this one's actually the moment. 👑

and FlitSize is defined by spec — CXL rev3.0 4.2.1, iykyk:

• a 68B flit is used up to 32GT/s
• above 32GT/s, the 256B flit size is used

then the FlitLatency gets converted to picoseconds. tiny units for a tiny number. periodt. 🌈

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👑 SEE ALSO 👑

• Kernel file ./drivers/cxl/core/pci.c
• cxl core pci(9)
• devm_cxl_add_dport_by_dev(9)
• cxl_hdm_decode_init(9)
• read_cdat_data(9)

go read the whole friend group, they're all iconic. 💜

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aaaand that's the page! this cutie lives in ./drivers/cxl/core, dated October 2026, and she's out here doing latency math on the PCIe link like the icon she is. mwah. 💅💖🧚