EMCFAN(4)

πŸ“¦ version 11.0, in nixpkgs unstable

🌸 NAME β€” EMCFAN(4) from the Kernel Interfaces Manual πŸŽ€

Okay so bestie, <pink>emcfan</pink> is the driver for the <purple>Microchip Technology EMC210x and EMC230x fan controllers via I2C bus</purple> πŸ’–. That’s the whole vibe. Periodt.

✨ SYNOPSIS ✨

emcfan* at iic? addr 0x2c
emcfan* at iic? addr 0x2d
emcfan* at iic? addr 0x2e
emcfan* at iic? addr 0x2f
emcfan* at iic? addr 0x4c
emcfan* at iic? addr 0x4d

πŸ’– DESCRIPTION πŸ’–

The <hotpink>emcfan</hotpink> driver supports the <purple>EMC210x</purple> family with these models: EMC2101, EMC2101-R, EMC2103-1, EMC2103-2, EMC2103-4, EMC2104, and EMC2106 ✨. And for the <purple>EMC230x</purple> family, it supports: EMC2301, EMC2302, EMC2303, and EMC2305 πŸ’….

All chips have one or more tachometers, and some of the chips have a number of temperature sensors and GPIO πŸŒ€. The <hotpink>emcfan</hotpink> driver provides <mint>envsys(4)</mint> framework measurements for the RPM as determined by the tachometers πŸ”₯.

If the chip has temperature sensors, the <mint>envsys(4)</mint> framework will provide an entry for every possible temperature sensor that a particular chip can support πŸ‘‘. GPIO support is provided by the <mint>gpio(4)</mint> framework and the pins can be accessed with the <mint>gpioctl(8)</mint> command 🫢.

The EMC fan controllers are arranged as a set of registers πŸ“š. These registers are accessed by a /dev device per attached chip. The program <mint>emcfanctl(8)</mint> makes use of this device and allows all valid registers for a particular chip to be read or written, and provides some higher level commands that allow the drive level and frequency divider for a particular fan to be adjusted βš™οΈ.

πŸ¦‹ GPIO πŸ¦‹

The EMC2103-2, EMC2103-4, EMC2104 and EMC2106 chips have gpio pins πŸ›. For the EMC2103-2 and EMC2103-4, these pins are only gpio and are not shared with any other function. For the EMC2104 and EMC2106, here is how the pins map to the altN flags in the <mint>gpio(4)</mint> framework πŸ’œ:

  • GPIO1 β€” ALT0: CLK_IN; ALT1: -
  • GPIO2 β€” ALT0: TACH2; ALT1: -
  • GPIO3 β€” ALT0: PWM2; ALT1: -
  • GPIO4 β€” ALT0: OVERT2#; ALT1: PWM3
  • GPIO5 β€” ALT0: OVERT3#; ALT1: PWM4
  • GPIO6 β€” ALT0: -; ALT1: -

🧠 SYSCTL VARIABLES 🧠

The following <mint>sysctl(8)</mint> variables are provided, bestie:

  • hw.emcfan0.debug β€” If the driver is compiled with EMCFAN_DEBUG, this node will appear and can be used to set the debugging level πŸ‘€.
  • hw.emcfan0.poles<n> β€” For a number of the chips in the two chip families, the tachometer calculation algorithm needs to know the number of poles that the tachometer has in order to calculate the RPM correctly 🌈. Usually this will be 2, but if the situation is otherwise, set this node to the number of poles that the particular fan has. The calculation is also affected by the number of edges present in the tachometer signal. The number of edges is set with the <mint>emcfanctl(8)</mint> command ⚑.
  • hw.emcfan0.ftach β€” Many of the chips in the two families have a pin that can be used to drive an alternative 32.767 kHz clock for the tachometers πŸ•°οΈ. The EMC2103-1, EMC2103-2 and EMC2103-4 does not have this alternative clock pin, and while it is likely that the chip is running at the default 32.000 kHz, it might not be. This variable lets one set an alternative clock. The units for this node are in Hz 🎡.
  • hw.emcfan0.vin4_temp_zone β€” The EMC2104 and EMC2106 have a special temperature sensor pin called VIN4, if this sensor is wired up, then this variable can be set to 1 and meaningful values will appear in the <mint>envsys(4)</mint> framework 🌑️.

πŸŽ€ FILES πŸŽ€

  • /dev/emcfanu β€” the device unit u file πŸ“.

πŸ‘‘ SEE ALSO πŸ‘‘

Go peek at these, iykyk:

⭐ HISTORY ⭐

The <hotpink>emcfan</hotpink> driver first appeared in NetBSD 11.0 πŸŽ‰.

🫢 AUTHORS 🫢

The <hotpink>emcfan</hotpink> driver was written by Brad Spencer <brad@anduin.eldar.org> πŸ’Œ.

πŸ’€ BUGS πŸ’€

The driver does not support the EMC2105 chip πŸ™ˆ.

While not exactly a bug, the driver does nothing with the alert interrupts that can be generated from many of the chips 😭. It would be more typical for this to be tied to a GPIO pin which can interrupt using CPU interrupts.

πŸ’Œ source/version: Debian Β· date: Feburary 19, 2025 β€” mwah, bestie πŸ’‹
πŸ“¦ where this page comes from