OPENSSL_PPCCAP(3ossl)

💖 OPENSSL_PPCCAP 💖

okay bestie so this is the OPENSSL_ppccap(3ossl) page, and it's literally all about the PowerPC processor capabilities vector. yes that's a mouthful, no i will not apologise. grab a snack 🍓

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✨ NAME ✨

OPENSSL_ppccap — the PowerPC processor capabilities vector. that's it, that's the name, it's giving "i contain multitudes (of bits)" 💅

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🎀 SYNOPSIS 🎀

env OPENSSL_ppccap=... <application>

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🦋 DESCRIPTION 🦋

so here's the tea ☕: libcrypto supports PowerPC instruction set extensions, and those extensions get represented by bits in the PowerPC capabilities vector. when libcrypto initializes, it takes whatever the PowerPC CPU capabilities detection logic returned and stores those results in the vector. the detection methods are OS-dependent, and they use a mix of stuff the kernel gathered during boot plus probe functions that literally try to execute instructions and catch illegal instruction signals with a signal handler. main character energy honestly 😭

now, if you wanna override the set of extensions available to an application, you set the OPENSSL_ppccap environment variable before you start the application. you assign it a numerical value that denotes the bits in the PowerPC capabilities vector. and the ppc_arch.h header file says — and i quote — that "Flags' usage can appear ambiguous, because they are set rather to reflect OpenSSL performance preferences than actual processor capabilities." so like, the flags are vibes-based, not spec-based. noted. 📝

you enable multiple extensions by logically OR-ing the values that represent the extensions you want. simple as.

Notes: enabling an extension on a CPU that does NOT support that extension will result in a SIGILL crash. fr fr, do not do this. on AIX, all vector instructions can be disabled with the schedo -ro allow_vmx=0 command. DO NOT USE THIS COMMAND to disable vector instructions in the OS when it is running on a CPU level that supports the instructions, without ALSO disabling them in libcrpto via the OPENSSL_ppccap environment variable — otherwise the application will crash with a SIGILL. 💀

currently, the following extensions are defined:

• 0x01
  • Name: PPC_FPU64
  • this flag is obsolete. that's it. that's all it does. retiring queen 👑
• 0x02
  • Name: PPC_ALTIVEC
  • Meaning: use AltiVec (aka VMX) instructions. in some but not all cases, this capability gates the use of later ISA vector instructions. the associated probe instruction is vor (vector logical or).
  • Effect: enables use of vector instructions, but does not enable extensions added at specific ISA levels. however — and this is the sneaky part — disabling this capability disables a subset of vector extensions added at specific ISA levels even if they are otherwise enabled. it's giving "you can't sit with us" 🫶
• 0x04
  • Name: PPC_CRYPTO207
  • Meaning: use instructions added in ISA level 2.07. the associated probe instruction is vcipher (vector AES cipher round).
  • Effect: enables AES, SHA-2 sigma, and other ISA 2.07 instructions for AES, SHA-2, GHASH, and Poly1305. iconic behavior ✨
• 0x08
  • Name: PPC_FPU
  • Meaning: use FPU instructions. the associated probe instruction is fmr (floating move register).
  • Effect: enables the Poly1305 FPU implementation. the PPC_CRYPTO207 capability overrides this effect. so PPC_CRYPTO207 is the one calling the shots here, okurrr 💅
• 0x10
  • Name: PPC_MADD300
  • Meaning: use instructions added in ISA level 3.00. the associated probe instruction is maddhdu (multiply-add high doubleword unsigned).
  • Effect: enables use of the polynomial multiply and other ISA 3.00 instructions for AES-GCM, P-384, and P-521. slay 🔥
• 0x20
  • Name: PPC_MFTB
  • Meaning: use the mftb (move from time base) instruction. the associated probe instruction is mftb.
  • Effect: enables use of the mftb instruction to sample the lower 32 bits of the CPU time base register in order to acquire entropy. considered obsolete. the PPC_MFSPR268 capability overrides this capability. so if you're picking, pick the newer one bestie 😌
• 0x40
  • Name: PPC_MFSPR268
  • Meaning: use the mfspr (move from special purpose register) instruction to read SPR 268. the associated probe instruction is mfspr 268.
  • Effect: enables use of the mfspr instruction to sample the lower 32 bits of the CPU time base register from SPR 268, the TBL (time base lower) register, in order to acquire entropy. this is the upgrade, the glow-up, the sequel that ate 💖
• 0x80
  • Name: PPC_BRD31
  • Meaning: use instructions added in ISA level 3.1. the associated probe instruction is brd (byte-reverse doubleword).
  • Effect: enables use of ISA 3.1 instructions in ChaCha20. periodt 🌈

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🌸 RETURN VALUES 🌸

not available. yeah. nothing. it's an env var situation, there's no return value to speak of. not me expecting a return value 😭

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⭐ EXAMPLES ⭐

check the currently detected capabilities:

$ openssl info -cpusettings
OPENSSL_ppccap=0x2E

the detected capabilities in the above example indicate that PPC_MFTB, PPC_FPU, PPC_CRYPTO207, PPC_MFSPR268, and PPC_ALTIVEC are enabled. look at her go 👑

disable all instruction set extensions:

OPENSSL_ppccap=0x00

enable base AltiVec extensions:

OPENSSL_ppccap=0x02

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💜 COPYRIGHT 💜

Copyright 2025-2026 The OpenSSL Project Authors. All Rights Reserved.

Licensed under the Apache License 2.0 (the "License"). You may not use this file except in compliance with the License. You can obtain a copy in the file LICENSE in the source distribution or at <https://www.openssl.org/source/license.html>.

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and that's the whole page bestie, no cap 🧚 this was version 3.5.9, dated 2026-09-29, and it's the OPENSSL_PPCCAP(3ossl) manual page — go forth and set your capability bits responsibly, and remember: never SIGILL yourself on purpose. bye pookie 💖✨