libcpuid(3)

📦

version 0.8.2 · 12 versions

💖 libcpuid — the LibCPUID situation 💖

okay so bestie, welcome to libcpuid(3) from the Library Functions Manual, and no cap, this one is a whole vibe. LibCPUID provides CPU identification. that's the whole gig. it looks at your processor and tells you what's up. iconic behavior fr fr.

✨ NAME ✨

libcpuid — LibCPUID. yes the name is literally the library. LibCPUID provides CPU identification. that's it, that's the mission statement, and honestly? slay.

🌸 SYNOPSIS 🌸

bestie, this is where it gets meaty. we got structures, we got macros, we got typedefs. buckle up 🎀

🦋 Data Structures 🦋

struct cpu_raw_data_t — just holds the raw CPUID data. unprocessed, unfiltered, straight from the source. it's giving raw data energy.
struct cpu_raw_data_array_t — an array of raw CPUID data. so like, many of the above. a whole squad of raw data.
struct cpu_sgx_t — carries the info about the SGX features of the processor. and then, for reasons known only to the original docs, it's immediately followed by the words:

Example usage:

...with nothing after it in this section. we love a cliffhanger 💀

struct x86_id_t — holds the x86 specific info. x86 girlies rise 💅
struct arm_id_t — holds the ARM specific info. ARM girlies also rise 🫶
struct cpu_id_t — the big one. this contains the recognized CPU features/info. main character struct energy 👑
struct system_id_t — contains the recognized features/info for all CPUs on the system. not just one, bestie. the whole roster.
struct cpu_mark_t — an internal structure, used in cpu_tsc_mark, cpu_tsc_unmark and cpu_clock_by_mark. internal!! so don't go poking it like it's yours 🙈
struct cpu_epc_t — this is literally the return value of cpuid_get_epc(). that's its entire lore.
struct cpu_list_t — a structure that holds a list of processor names. a lil roster of CPU names, adorable.

🌈 Macros 🌈

#define LIBCPUID_DEPRECATED(message) — the deprecation marker macro, takes a message. it's the library's way of saying "this one is old, bestie, please move on".
#define NUM_CPU_VENDORS NUM_CPU_VENDORS — yes it defines itself to itself. no, we are not going to explain it. it is what it is. periodt.
#define NUM_CPU_ARCHITECTURES NUM_CPU_ARCHITECTURES — same situation, different name. iconic honestly.
#define NUM_FEATURE_LEVELS NUM_FEATURE_LEVELS — once again defining itself. self-love, we stan.
#define NUM_CPU_PURPOSES NUM_CPU_PURPOSES — yep. itself. again. consistency is a virtue.
#define NUM_HYPERVISOR_VENDORS NUM_HYPERVISOR_VENDORS — and another one. the self-definition streak is unmatched 🔥
#define CPU_INVALID_VALUE 0x3fffffff — the "this value is invalid" sentinel, and its exact value is 0x3fffffff. memorize it or whatever, it'll come back.

⭐ Typedefs ⭐

typedef void(* libcpuid_warn_fn_t) (const char *msg) — a function pointer type for warning callbacks. it takes a const char *msg and returns void. so if the library needs to warn you about something, this is the shape of the function it'll call to do it. very "hey bestie, heads up" of it.

okay that's the structures, macros and typedefs wrapped. the rest of this manual is long and we're only on part 1, so keep scrolling bestie, there is SO much more 💜

✨ Enumerations ✨

okay bestie, this is the big one — all the enums the library hands you. every value listed below is exactly as it is in the header, no cap. 💅

`enum cpu_vendor_t`

enum cpu_vendor_t { VENDOR_INTEL = 0, VENDOR_AMD, VENDOR_CYRIX,
    VENDOR_NEXGEN, VENDOR_TRANSMETA, VENDOR_UMC, VENDOR_CENTAUR,
    VENDOR_RISE, VENDOR_SIS, VENDOR_NSC, VENDOR_HYGON, VENDOR_ARM,
    VENDOR_BROADCOM, VENDOR_CAVIUM, VENDOR_DEC, VENDOR_FUJITSU,
    VENDOR_HISILICON, VENDOR_INFINEON, VENDOR_FREESCALE, VENDOR_NVIDIA,
    VENDOR_APM, VENDOR_QUALCOMM, VENDOR_SAMSUNG, VENDOR_MARVELL,
    VENDOR_APPLE, VENDOR_FARADAY, VENDOR_MICROSOFT, VENDOR_PHYTIUM,
    VENDOR_AMPERE, NUM_CPU_VENDORS, VENDOR_UNKNOWN = -1 }

the CPU vendor, figured out from the Vendor String. that's the vibe — libcpuid peeks at the string and goes "oh you're an VENDOR_APPLE bestie, iconic". VENDOR_UNKNOWN is -1 so it's lowkey the "idk her" option. 🍓

`enum cpu_architecture_t`

enum cpu_architecture_t { ARCHITECTURE_X86 = 0, ARCHITECTURE_ARM,
    NUM_CPU_ARCHITECTURES, ARCHITECTURE_UNKNOWN = -1 }

the CPU architecture. yes it's short. sometimes the queen keeps it simple. ARCHITECTURE_UNKNOWN is -1 again, the classic escape hatch. 🦋

`enum cpu_feature_level_t`

enum cpu_feature_level_t { FEATURE_LEVEL_I386, FEATURE_LEVEL_I486,
    FEATURE_LEVEL_I586, FEATURE_LEVEL_I686, FEATURE_LEVEL_X86_64_V1,
    FEATURE_LEVEL_X86_64_V2, FEATURE_LEVEL_X86_64_V3,
    FEATURE_LEVEL_X86_64_V4, FEATURE_LEVEL_ARM_V1 = 100,
    FEATURE_LEVEL_ARM_V2, FEATURE_LEVEL_ARM_V3, FEATURE_LEVEL_ARM_V4,
    FEATURE_LEVEL_ARM_V4T, FEATURE_LEVEL_ARM_V5, FEATURE_LEVEL_ARM_V5T,
    FEATURE_LEVEL_ARM_V5TE, FEATURE_LEVEL_ARM_V5TEJ,
    FEATURE_LEVEL_ARM_V6, FEATURE_LEVEL_ARM_V6_M,
    FEATURE_LEVEL_ARM_V7_A, FEATURE_LEVEL_ARM_V7_M,
    FEATURE_LEVEL_ARM_V7_R, FEATURE_LEVEL_ARM_V7E_M,
    FEATURE_LEVEL_ARM_V8_0_A, FEATURE_LEVEL_ARM_V8_0_M,
    FEATURE_LEVEL_ARM_V8_0_R, FEATURE_LEVEL_ARM_V8_1_A,
    FEATURE_LEVEL_ARM_V8_1_M, FEATURE_LEVEL_ARM_V8_2_A,
    FEATURE_LEVEL_ARM_V8_3_A, FEATURE_LEVEL_ARM_V8_4_A,
    FEATURE_LEVEL_ARM_V8_5_A, FEATURE_LEVEL_ARM_V8_6_A,
    FEATURE_LEVEL_ARM_V8_7_A, FEATURE_LEVEL_ARM_V8_8_A,
    FEATURE_LEVEL_ARM_V8_9_A, FEATURE_LEVEL_ARM_V9_0_A,
    FEATURE_LEVEL_ARM_V9_1_A, FEATURE_LEVEL_ARM_V9_2_A,
    FEATURE_LEVEL_ARM_V9_3_A, FEATURE_LEVEL_ARM_V9_4_A,
    FEATURE_LEVEL_ARM_V9_5_A, NUM_FEATURE_LEVELS, FEATURE_LEVEL_UNKNOWN
    = -1 }

the CPU feature level! notice how x86 starts at 0 and ARM starts at 100? that's a deliberate little gap so the two families never beef over numbers. main character energy. and FEATURE_LEVEL_UNKNOWN = -1 holds down the "we don't know her" corner. 💜

`enum cpu_purpose_t`

enum cpu_purpose_t { PURPOSE_GENERAL = 0, PURPOSE_PERFORMANCE,
    PURPOSE_EFFICIENCY, PURPOSE_LP_EFFICIENCY, PURPOSE_U_PERFORMANCE,
    NUM_CPU_PURPOSES }

the CPU purpose. like, is this core here for general stuff, for raw performance, for efficiency, for low-power efficiency, or for ultra-performance? it's giving big-little core lore and honestly we're obsessed. 🔥

`enum hypervisor_vendor_t`

enum hypervisor_vendor_t { HYPERVISOR_NONE = 0, HYPERVISOR_BHYVE,
    HYPERVISOR_HYPERV, HYPERVISOR_KVM, HYPERVISOR_PARALLELS,
    HYPERVISOR_QEMU, HYPERVISOR_VIRTUALBOX, HYPERVISOR_VMWARE,
    HYPERVISOR_XEN, NUM_HYPERVISOR_VENDORS, HYPERVISOR_UNKNOWN = -1 }

the hypervisor vendor, guessed from the CPU_FEATURE_HYPERVISOR flag. HYPERVISOR_NONE = 0 means you're on bare metal, periodt. HYPERVISOR_UNKNOWN = -1 is the "couldn't tell, she's mysterious" slot. 🧚

`enum cpu_feature_t`

bestie. breathe. this one is long. it's the CPU feature identifiers and no, I'm not skipping a single one, the facts stay facts. 🫶

enum cpu_feature_t { CPU_FEATURE_FPU = 0, CPU_FEATURE_VME,
    CPU_FEATURE_DE, CPU_FEATURE_PSE, CPU_FEATURE_TSC, CPU_FEATURE_MSR,
    CPU_FEATURE_PAE, CPU_FEATURE_MCE, CPU_FEATURE_CX8, CPU_FEATURE_APIC,
    CPU_FEATURE_MTRR, CPU_FEATURE_SEP, CPU_FEATURE_PGE, CPU_FEATURE_MCA,
    CPU_FEATURE_CMOV, CPU_FEATURE_PAT, CPU_FEATURE_PSE36,
    CPU_FEATURE_PN, CPU_FEATURE_CLFLUSH, CPU_FEATURE_DTS,
    CPU_FEATURE_ACPI, CPU_FEATURE_MMX, CPU_FEATURE_FXSR,
    CPU_FEATURE_SSE, CPU_FEATURE_SSE2, CPU_FEATURE_SS, CPU_FEATURE_HT,
    CPU_FEATURE_TM, CPU_FEATURE_IA64, CPU_FEATURE_PBE, CPU_FEATURE_PNI,
    CPU_FEATURE_PCLMUL, CPU_FEATURE_DTS64, CPU_FEATURE_MONITOR,
    CPU_FEATURE_DS_CPL, CPU_FEATURE_VMX, CPU_FEATURE_SMX,
    CPU_FEATURE_EST, CPU_FEATURE_TM2, CPU_FEATURE_SSSE3,
    CPU_FEATURE_CID, CPU_FEATURE_CX16, CPU_FEATURE_XTPR,
    CPU_FEATURE_PDCM, CPU_FEATURE_DCA, CPU_FEATURE_SSE4_1,
    CPU_FEATURE_SSE4_2, CPU_FEATURE_SYSCALL, CPU_FEATURE_XD,
    CPU_FEATURE_MOVBE, CPU_FEATURE_POPCNT, CPU_FEATURE_AES,
    CPU_FEATURE_XSAVE, CPU_FEATURE_OSXSAVE, CPU_FEATURE_AVX,
    CPU_FEATURE_MMXEXT, CPU_FEATURE_3DNOW, CPU_FEATURE_3DNOWEXT,
    CPU_FEATURE_NX, CPU_FEATURE_FXSR_OPT, CPU_FEATURE_RDTSCP,
    CPU_FEATURE_LM, CPU_FEATURE_LAHF_LM, CPU_FEATURE_CMP_LEGACY,
    CPU_FEATURE_SVM, CPU_FEATURE_ABM, CPU_FEATURE_MISALIGNSSE,
    CPU_FEATURE_SSE4A, CPU_FEATURE_3DNOWPREFETCH, CPU_FEATURE_OSVW,
    CPU_FEATURE_IBS, CPU_FEATURE_SSE5, CPU_FEATURE_SKINIT,
    CPU_FEATURE_WDT, CPU_FEATURE_TS, CPU_FEATURE_FID, CPU_FEATURE_VID,
    CPU_FEATURE_TTP, CPU_FEATURE_TM_AMD, CPU_FEATURE_STC,
    CPU_FEATURE_100MHZSTEPS, CPU_FEATURE_HWPSTATE,
    CPU_FEATURE_CONSTANT_TSC, CPU_FEATURE_XOP, CPU_FEATURE_FMA3,
    CPU_FEATURE_FMA4, CPU_FEATURE_TBM, CPU_FEATURE_F16C,
    CPU_FEATURE_RDRAND, CPU_FEATURE_X2APIC, CPU_FEATURE_CPB,
    CPU_FEATURE_APERFMPERF, CPU_FEATURE_PFI, CPU_FEATURE_PA,
    CPU_FEATURE_AVX2, CPU_FEATURE_BMI1, CPU_FEATURE_BMI2,
    CPU_FEATURE_HLE, CPU_FEATURE_RTM, CPU_FEATURE_AVX512F,
    CPU_FEATURE_AVX512DQ, CPU_FEATURE_AVX512PF, CPU_FEATURE_AVX512ER,
    CPU_FEATURE_AVX512CD, CPU_FEATURE_SHA_NI, CPU_FEATURE_AVX512BW,
    CPU_FEATURE_AVX512VL, CPU_FEATURE_SGX, CPU_FEATURE_RDSEED,
    CPU_FEATURE_ADX, CPU_FEATURE_AVX512VNNI, CPU_FEATURE_AVX512VBMI,
    CPU_FEATURE_AVX512VBMI2, CPU_FEATURE_HYPERVISOR, CPU_FEATURE_SWAP,
    CPU_FEATURE_THUMB, CPU_FEATURE_ADVMULTU, CPU_FEATURE_ADVMULTS,
    CPU_FEATURE_JAZELLE, CPU_FEATURE_DEBUGV6, CPU_FEATURE_DEBUGV6P1,
    CPU_FEATURE_THUMB2, CPU_FEATURE_DEBUGV7, CPU_FEATURE_DEBUGV7P1,
    CPU_FEATURE_THUMBEE, CPU_FEATURE_DIVIDE, CPU_FEATURE_LPAE,
    CPU_FEATURE_PMUV1, CPU_FEATURE_PMUV2, CPU_FEATURE_ASID16,
    CPU_FEATURE_ADVSIMD, CPU_FEATURE_CRC32, CPU_FEATURE_CSV2_1P1,
    CPU_FEATURE_CSV2_1P2, CPU_FEATURE_CSV2_2, CPU_FEATURE_CSV2_3,
    CPU_FEATURE_DOUBLELOCK, CPU_FEATURE_ETS2, CPU_FEATURE_FP,
    CPU_FEATURE_MIXEDEND, CPU_FEATURE_MIXEDENDEL0, CPU_FEATURE_PMULL,
    CPU_FEATURE_PMUV3, CPU_FEATURE_SHA1, CPU_FEATURE_SHA256,
    CPU_FEATURE_NTLBPA, CPU_FEATURE_HAFDBS, CPU_FEATURE_HPDS,
    CPU_FEATURE_LOR, CPU_FEATURE_LSE, CPU_FEATURE_PAN,
    CPU_FEATURE_PMUV3P1, CPU_FEATURE_RDM, CPU_FEATURE_VHE,
    CPU_FEATURE_VMID16, CPU_FEATURE_AA32HPD, CPU_FEATURE_AA32I8MM,
    CPU_FEATURE_DPB, CPU_FEATURE_DEBUGV8P2, CPU_FEATURE_F32MM,
    CPU_FEATURE_F64MM, CPU_FEATURE_FP16, CPU_FEATURE_HPDS2,
    CPU_FEATURE_I8MM, CPU_FEATURE_IESB, CPU_FEATURE_LPA,
    CPU_FEATURE_LSMAOC, CPU_FEATURE_LVA, CPU_FEATURE_PAN2,
    CPU_FEATURE_RAS, CPU_FEATURE_SHA3, CPU_FEATURE_SHA512,
    CPU_FEATURE_SM3, CPU_FEATURE_SM4, CPU_FEATURE_SPE, CPU_FEATURE_SVE,
    CPU_FEATURE_TTCNP, CPU_FEATURE_UAO, CPU_FEATURE_XNX,
    CPU_FEATURE_CCIDX, CPU_FEATURE_CONSTPACFIELD, CPU_FEATURE_EPAC,
    CPU_FEATURE_FCMA, CPU_FEATURE_FPAC, CPU_FEATURE_FPACCOMBINE,
    CPU_FEATURE_JSCVT, CPU_FEATURE_LRCPC, CPU_FEATURE_PACIMP,
    CPU_FEATURE_PACQARMA3, CPU_FEATURE_PACQARMA5, CPU_FEATURE_PAUTH,
    CPU_FEATURE_SPEV1P1, CPU_FEATURE_AMUV1, CPU_FEATURE_BBM,
    CPU_FEATURE_DIT, CPU_FEATURE_DEBUGV8P4, CPU_FEATURE_DOTPROD,
    CPU_FEATURE_DOUBLEFAULT, CPU_FEATURE_FHM, CPU_FEATURE_FLAGM,
    CPU_FEATURE_IDST, CPU_FEATURE_LRCPC2, CPU_FEATURE_LSE2,
    CPU_FEATURE_MPAM, CPU_FEATURE_PMUV3P4, CPU_FEATURE_RASV1P1,
    CPU_FEATURE_S2FWB, CPU_FEATURE_SEL2, CPU_FEATURE_TLBIOS,
    CPU_FEATURE_TLBIRANGE, CPU_FEATURE_TRF, CPU_FEATURE_TTL,
    CPU_FEATURE_TTST, CPU_FEATURE_BTI, CPU_FEATURE_CSV2,
    CPU_FEATURE_CSV3, CPU_FEATURE_DPB2, CPU_FEATURE_E0PD,
    CPU_FEATURE_EVT, CPU_FEATURE_EXS, CPU_FEATURE_FRINTTS,
    CPU_FEATURE_FLAGM2, CPU_FEATURE_MTE, CPU_FEATURE_MTE2,
    CPU_FEATURE_PMUV3P5, CPU_FEATURE_RNG, CPU_FEATURE_RNG_TRAP,
    CPU_FEATURE_SB, CPU_FEATURE_SPECRES, CPU_FEATURE_SSBS,
    CPU_FEATURE_SSBS2, CPU_FEATURE_AA32BF16, CPU_FEATURE_AMUV1P1,
    CPU_FEATURE_BF16, CPU_FEATURE_DGH, CPU_FEATURE_ECV, CPU_FEATURE_FGT,
    CPU_FEATURE_HPMN0, CPU_FEATURE_MPAMV0P1, CPU_FEATURE_MPAMV1P1,
    CPU_FEATURE_MTPMU, CPU_FEATURE_PAUTH2, CPU_FEATURE_TWED,
    CPU_FEATURE_AFP, CPU_FEATURE_EBF16, CPU_FEATURE_HCX,
    CPU_FEATURE_LPA2, CPU_FEATURE_LS64, CPU_FEATURE_LS64_ACCDATA,
    CPU_FEATURE_LS64_V, CPU_FEATURE_MTE3, CPU_FEATURE_MTE_ASYM_FAULT,
    CPU_FEATURE_PAN3, CPU_FEATURE_PMUV3P7, CPU_FEATURE_RPRES,
    CPU_FEATURE_SPEV1P2, CPU_FEATURE_WFXT, CPU_FEATURE_XS,
    CPU_FEATURE_CMOW, CPU_FEATURE_DEBUGV8P8, CPU_FEATURE_HBC,
    CPU_FEATURE_MOPS, CPU_FEATURE_NMI, CPU_FEATURE_PMUV3P8,
    CPU_FEATURE_SCTLR2, CPU_FEATURE_SPEV1P3, CPU_FEATURE_TCR2,
    CPU_FEATURE_TIDCP1, CPU_FEATURE_ADERR, CPU_FEATURE_AIE,
    CPU_FEATURE_ANERR, CPU_FEATURE_ATS1A, CPU_FEATURE_CLRBHB,
    CPU_FEATURE_CSSC, CPU_FEATURE_DEBUGV8P9, CPU_FEATURE_DOUBLEFAULT2,
    CPU_FEATURE_ECBHB, CPU_FEATURE_FGT2, CPU_FEATURE_HAFT,
    CPU_FEATURE_LRCPC3, CPU_FEATURE_MTE4, CPU_FEATURE_MTE_ASYNC,
    CPU_FEATURE_MTE_CANONICAL_TAGS, CPU_FEATURE_MTE_NO_ADDRESS_TAGS,
    CPU_FEATURE_MTE_PERM, CPU_FEATURE_MTE_STORE_ONLY,
    CPU_FEATURE_MTE_TAGGED_FAR, CPU_FEATURE_PFAR,
    CPU_FEATURE_PMUV3_ICNTR, CPU_FEATURE_PMUV3_SS, CPU_FEATURE_PMUV3P9,
    CPU_FEATURE_PRFMSLC, CPU_FEATURE_RASV2, CPU_FEATURE_RPRFM,
    CPU_FEATURE_S1PIE, CPU_FEATURE_S1POE, CPU_FEATURE_S2PIE,
    CPU_FEATURE_S2POE, CPU_FEATURE_SPECRES2, CPU_FEATURE_SPE_DPFZS,
    CPU_FEATURE_SPEV1P4, CPU_FEATURE_SPMU, CPU_FEATURE_THE,
    CPU_FEATURE_SVE2, CPU_FEATURE_SVE_AES, CPU_FEATURE_SVE_BITPERM,
    CPU_FEATURE_SVE_PMULL128, CPU_FEATURE_SVE_SHA3, CPU_FEATURE_SVE_SM4,
    CPU_FEATURE_TME, CPU_FEATURE_TRBE, CPU_FEATURE_BRBE,
    CPU_FEATURE_RME, CPU_FEATURE_SME, CPU_FEATURE_SME_F64F64,
    CPU_FEATURE_SME_FA64, CPU_FEATURE_SME_I16I64, CPU_FEATURE_BRBEV1P1,
    CPU_FEATURE_MEC, CPU_FEATURE_SME2, CPU_FEATURE_ABLE,
    CPU_FEATURE_BWE, CPU_FEATURE_D128, CPU_FEATURE_EBEP,
    CPU_FEATURE_GCS, CPU_FEATURE_ITE, CPU_FEATURE_LSE128,
    CPU_FEATURE_LVA3, CPU_FEATURE_SEBEP, CPU_FEATURE_SME2P1,
    CPU_FEATURE_SME_F16F16, CPU_FEATURE_SVE2P1, CPU_FEATURE_SVE_B16B16,
    CPU_FEATURE_SYSINSTR128, CPU_FEATURE_SYSREG128,
    CPU_FEATURE_TRBE_EXT, CPU_FEATURE_ASID2, CPU_FEATURE_BWE2,
    CPU_FEATURE_CPA, CPU_FEATURE_CPA2, CPU_FEATURE_E2H0,
    CPU_FEATURE_E3DSE, CPU_FEATURE_ETS3, CPU_FEATURE_FAMINMAX,
    CPU_FEATURE_FGWTE3, CPU_FEATURE_FP8, CPU_FEATURE_FP8DOT2,
    CPU_FEATURE_FP8DOT4, CPU_FEATURE_FP8FMA, CPU_FEATURE_FPMR,
    CPU_FEATURE_HACDBS, CPU_FEATURE_HDBSS, CPU_FEATURE_LUT,
    CPU_FEATURE_PAUTH_LR, CPU_FEATURE_RME_GPC2, CPU_FEATURE_SME_F8F16,
    CPU_FEATURE_SME_F8F32, CPU_FEATURE_SME_LUTV2, CPU_FEATURE_SPMU2,
    CPU_FEATURE_SSVE_FP8DOT2, CPU_FEATURE_SSVE_FP8DOT4,
    CPU_FEATURE_SSVE_FP8FMA, CPU_FEATURE_STEP2, CPU_FEATURE_TLBIW,
    NUM_CPU_FEATURES }

like… that's the CPU feature identifiers, all of them, from your x86 classics (CPU_FEATURE_FPU = 0, CPU_FEATURE_SSE, CPU_FEATURE_AVX, the whole CPU_FEATURE_AVX512* squad) all the way through the ARM world (CPU_FEATURE_THUMB, CPU_FEATURE_SVE*, CPU_FEATURE_SME*, the CPU_FEATURE_MTE* family, and every DEBUGV8P*/DEBUGV8P9 bestie). CPU_FEATURE_HYPERVISOR is in there too — that's the one that snitches on whether you're running under a hypervisor. NUM_CPU_FEATURES is the counter at the end so you can loop without guessing. iykyk. 💀

fr fr: this enum is huge, so don't hardcode counts — use NUM_CPU_FEATURES and let it do the math for you.

`enum cpu_hint_t`

enum cpu_hint_t { CPU_HINT_SSE_SIZE_AUTH = 0, NUM_CPU_HINTS }

CPU detection hints identifiers. tiny enum, big responsibility. CPU_HINT_SSE_SIZE_AUTH is the hint you flip when you want the SSE size reported as authoritative. 🎀

`enum cpu_sgx_feature_t`

enum cpu_sgx_feature_t { INTEL_SGX1, INTEL_SGX2, NUM_SGX_FEATURES }

SGX features flags. just INTEL_SGX1, INTEL_SGX2, and NUM_SGX_FEATURES to keep count. short, sweet, iconic. ⭐

`enum cpu_error_t`

enum cpu_error_t { ERR_OK = 0, ERR_NO_CPUID = -1, ERR_NO_RDTSC = -2,
    ERR_NO_MEM = -3, ERR_OPEN = -4, ERR_BADFMT = -5, ERR_NOT_IMP = -6,
    ERR_CPU_UNKN = -7, ERR_NO_RDMSR = -8, ERR_NO_DRIVER = -9,
    ERR_NO_PERMS = -10, ERR_EXTRACT = -11, ERR_HANDLE = -12, ERR_INVMSR
    = -13, ERR_INVCNB = -14, ERR_HANDLE_R = -15, ERR_INVRANGE = -16,
    ERR_NOT_FOUND = -17, ERR_IOCTL = -18, ERR_REQUEST = -19 }

these are the common library error codes — the whole mood ring of things that can go wrong. ERR_OK = 0 is the slay, everything else is negative and each one is a different flavour of "bestie, no". 😭

ERR_OK = 0 — we're so back 🫶
ERR_NO_CPUID = -1 — no CPUID instruction available
ERR_NO_RDTSC = -2 — no RDTSC
ERR_NO_MEM = -3 — out of memory
ERR_OPEN = -4 — couldn't open something
ERR_BADFMT = -5 — the format was not it
ERR_NOT_IMP = -6 — not implemented
ERR_CPU_UNKN = -7 — unknown CPU
ERR_NO_RDMSR = -8 — no RDMSR
ERR_NO_DRIVER = -9 — no driver
ERR_NO_PERMS = -10 — no permissions
ERR_EXTRACT = -11 — extraction failed
ERR_HANDLE = -12 — handle issue
ERR_INVMSR = -13 — invalid MSR
ERR_INVCNB = -14 — invalid CPU number
ERR_HANDLE_R = -15 — handle read issue
ERR_INVRANGE = -16 — invalid range
ERR_NOT_FOUND = -17 — not found, she's not here
ERR_IOCTL = -18 — ioctl issue
ERR_REQUEST = -19 — request issue

ngl, when a call comes back negative, go check this list before you spiral — the number tells you exactly which kind of bad day it is. ✨

...and there's one more little enum chillin' in the synopsis before we get to the fun stuff:

enum cpu_msrinfo_request_t { INFO_MPERF, INFO_APERF,
    INFO_MIN_MULTIPLIER, INFO_CUR_MULTIPLIER, INFO_MAX_MULTIPLIER,
    INFO_TEMPERATURE, INFO_THROTTLING, INFO_VOLTAGE, INFO_BCLK,
    INFO_BUS_CLOCK }

💫 FUNCTIONS 💫

okay bestie, this is the big one — every single function libcpuid hands you, no cap. take a deep breath, we got this 🫶

int cpuid_get_total_cpus (void) — hands you the total count of logical CPU threads. and yes, it still works even if CPUID itself isn't a thing on this machine. iconic.
int cpuid_present (void) — vibe check: is the CPUID instruction even supported here? 👀
void cpu_exec_cpuid (uint32_t eax, uint32_t *regs) — literally runs the CPUID instruction for you.
void cpu_exec_cpuid_ext (uint32_t *regs) — same energy, but it runs CPUID using the input registers you already handed it.
int cpuid_get_raw_data (struct cpu_raw_data_t *data) — scoops the raw CPUID data off the current CPU ✨
int cpuid_get_raw_data_core (struct cpu_raw_data_t *data, logical_cpu_t logical_cpu) — same, but for the specific CPU you name. main character selection energy 💅
int cpuid_get_all_raw_data (struct cpu_raw_data_array_t *data) — grabs the raw CPUID data from every CPU. all of them. periodt.
int cpuid_serialize_raw_data (struct cpu_raw_data_t *data, const char *filename) — writes that raw CPUID data out to a text file.
int cpuid_serialize_all_raw_data (struct cpu_raw_data_array_t *data, const char *filename) — writes all the raw CPUID data out to a text file.
int cpuid_deserialize_raw_data (struct cpu_raw_data_t *data, const char *filename) — reads raw CPUID data back in from a file.
int cpuid_deserialize_all_raw_data (struct cpu_raw_data_array_t *data, const char *filename) — reads all the raw CPUID data back in from a file.
int cpu_identify (struct cpu_raw_data_t *raw, struct cpu_id_t *data) — the moment of truth: identifies the CPU 🔍
int cpu_identify_all (struct cpu_raw_data_array_t *raw_array, struct system_id_t *system) — identifies every CPU in the house, no one left out 🫶
int cpu_request_core_type (cpu_purpose_t purpose, struct cpu_raw_data_array_t *raw_array, struct cpu_id_t *data) — identifies a specific CPU type for you.
const char * cpu_architecture_str (cpu_architecture_t architecture) — gives you the short, cute text version of a CPU architecture.
const char * cpu_feature_level_str (cpu_feature_level_t level) — short text version of a CPU feature level.
const char * cpu_purpose_str (cpu_purpose_t purpose) — short text version of a CPU purpose.
char * affinity_mask_str_r (cpu_affinity_mask_t *affinity_mask, char *buffer, uint32_t buffer_len) — turns a CPU affinity mask into readable text, and it's thread-safe so you can flex it anywhere 💪
char * affinity_mask_str (cpu_affinity_mask_t *affinity_mask) — turns a CPU affinity mask into readable text (non-thread-safe edition).
const char * cpu_feature_str (cpu_feature_t feature) — short text version of a CPU flag.
const char * cpuid_error (void) — tells you, in words, what the last error was. emotional support error message 😭
void cpu_rdtsc (uint64_t *result) — executes RDTSC. that's it, that's the function.
void cpu_tsc_mark (struct cpu_mark_t *mark) — stores the TSC and timing info into your mark.
void cpu_tsc_unmark (struct cpu_mark_t *mark) — crunches the TSC and timing difference for you.
int cpu_clock_by_mark (struct cpu_mark_t *mark) — calculates the CPU clock from that mark.
int cpu_clock_by_os (void) — the CPU clock, straight from what the OS is claiming.
int cpu_clock_measure (int millis, int quad_check) — measures the CPU clock frequency the hands-on way.
int cpu_clock_by_ic (int millis, int runs) — measures the CPU clock frequency using instruction-counting.
int cpu_clock_by_tsc (struct cpu_raw_data_t *raw) — measures the CPU clock frequency using the TSC frequency that CPUID reports.
int cpu_clock (void) — the CPU clock frequency, all-in-one method, the lazy-girl slay ✨
struct cpu_epc_t cpuid_get_epc (int index, const struct cpu_raw_data_t *raw) — fetches the tea on an EPC (Enclave Page Cache) area.
const char * cpuid_lib_version (void) — tells you which libcpuid version you're running.
libcpuid_warn_fn_t cpuid_set_warn_function (libcpuid_warn_fn_t warn_fun) — sets the function used for printing warnings.
void cpuid_set_verbosiness_level (int level) — sets the verbosiness level. (yes, that's the actual spelling, we do not fix it, we respect it 💜)
cpu_vendor_t cpuid_get_vendor (void) — gets the CPU vendor from CPUID, from the current CPU.
hypervisor_vendor_t cpuid_get_hypervisor (struct cpu_raw_data_t *raw, struct cpu_id_t *data) — gets the hypervisor vendor from CPUID, from the current CPU.
void cpuid_get_cpu_list (cpu_vendor_t vendor, struct cpu_list_t *list) — gives you a list of every known CPU name from one specific vendor 📋
void cpuid_free_cpu_list (struct cpu_list_t *list) — frees a CPU list. clean up after yourself bestie 🧹
void cpuid_free_raw_data_array (struct cpu_raw_data_array_t *raw_array) — frees a raw array.
void cpuid_free_system_id (struct system_id_t *system) — frees a system ID type.
struct msr_driver_t * cpu_msr_driver_open (void) — starts/opens the driver you need in order to read MSRs (Model Specific Registers).
struct msr_driver_t * cpu_msr_driver_open_core (unsigned core_num) — basically cpu_msr_driver_open, except it takes one parameter.
int cpu_rdmsr (struct msr_driver_t *handle, uint32_t msr_index, uint64_t *result) — reads a Model-Specific Register (MSR).
int cpu_rdmsr_range (struct msr_driver_t *handle, uint32_t msr_index, uint8_t highbit, uint8_t lowbit, uint64_t *result) — like cpu_rdmsr, but it pulls out just a range of bits.
int cpu_msrinfo (struct msr_driver_t *handle, cpu_msrinfo_request_t which) — reads extended CPU info out of the Model-Specific Registers.
int msr_serialize_raw_data (struct msr_driver_t *handle, const char *filename) — writes the raw MSR data out to a text file.
int cpu_msr_driver_close (struct msr_driver_t *handle) — closes an open MSR driver. bye bye driver 🦋

📖 DETAILED DESCRIPTION 📖

LibCPUID provides CPU identification. yes, that's literally it — the whole vibe in one sentence and honestly? iconic. 👑

🔍 ENUMERATION TYPE DOCUMENTATION 🔍

🏗️ enum cpu_architecture_t

CPU architecture. the big picture of what kind of brain your silicon has:

ARCHITECTURE_X86 — x86 CPU
ARCHITECTURE_ARM — ARM CPU
NUM_CPU_ARCHITECTURES — valid CPU architecture ids go 0..NUM_CPU_ARCHITECTURES - 1

🚨 enum cpu_error_t

describes the common library error codes. when things go wrong, it's one of these:

ERR_OK — No error 🎉
ERR_NO_CPUID — CPUID instruction is not supported
ERR_NO_RDTSC — RDTSC instruction is not supported
ERR_NO_MEM — Memory allocation failed
ERR_OPEN — File open operation failed
ERR_BADFMT — Bad file format
ERR_NOT_IMP — Not implemented
ERR_CPU_UNKN — Unsupported processor
ERR_NO_RDMSR — RDMSR instruction is not supported
ERR_NO_DRIVER — RDMSR driver error (generic)
ERR_NO_PERMS — No permissions to install RDMSR driver
ERR_EXTRACT — Cannot extract RDMSR driver (read only media?)
ERR_HANDLE — Bad handle
ERR_INVMSR — Invalid MSR
ERR_INVCNB — Invalid core number
ERR_HANDLE_R — Error on handle read
ERR_INVRANGE — Invalid given range
ERR_NOT_FOUND — Requested type not found
ERR_IOCTL — Error on ioctl
ERR_REQUEST — Invalid request

📶 enum cpu_feature_level_t

CPU feature level. it's giving tier list, and here's every tier:

FEATURE_LEVEL_I386 — i386
FEATURE_LEVEL_I486 — i486
FEATURE_LEVEL_I586 — i586
FEATURE_LEVEL_I686 — i686
FEATURE_LEVEL_X86_64_V1 — x86-64-v1
FEATURE_LEVEL_X86_64_V2 — x86-64-v2
FEATURE_LEVEL_X86_64_V3 — x86-64-v3
FEATURE_LEVEL_X86_64_V4 — x86-64-v4
FEATURE_LEVEL_ARM_V1 — ARMv1
FEATURE_LEVEL_ARM_V2 — ARMv2
FEATURE_LEVEL_ARM_V3 — ARMv3
FEATURE_LEVEL_ARM_V4 — ARMv4
FEATURE_LEVEL_ARM_V4T — ARMv4T
FEATURE_LEVEL_ARM_V5 — ARMv5 (obsolete) 💀
FEATURE_LEVEL_ARM_V5T — ARMv5T
FEATURE_LEVEL_ARM_V5TE — ARMv5TE
FEATURE_LEVEL_ARM_V5TEJ — ARMv5TEJ
FEATURE_LEVEL_ARM_V6 — ARMv6
FEATURE_LEVEL_ARM_V6_M — ARMv6-M
FEATURE_LEVEL_ARM_V7_A — ARMv7-A
FEATURE_LEVEL_ARM_V7_M — ARMv7-M
FEATURE_LEVEL_ARM_V7_R — ARMv7-R
FEATURE_LEVEL_ARM_V7E_M — ARMv7E-M
FEATURE_LEVEL_ARM_V8_0_A — ARMv8.0-A
FEATURE_LEVEL_ARM_V8_0_M — ARMv8.0-M
FEATURE_LEVEL_ARM_V8_0_R — ARMv8.0-R
FEATURE_LEVEL_ARM_V8_1_A — ARMv8.1-A
FEATURE_LEVEL_ARM_V8_1_M — ARMv8.1-M
FEATURE_LEVEL_ARM_V8_2_A — ARMv8.2-A
FEATURE_LEVEL_ARM_V8_3_A — ARMv8.3-A
FEATURE_LEVEL_ARM_V8_4_A — ARMv8.4-A
FEATURE_LEVEL_ARM_V8_5_A — ARMv8.5-A
FEATURE_LEVEL_ARM_V8_6_A — ARMv8.6-A
FEATURE_LEVEL_ARM_V8_7_A — ARMv8.7-A
FEATURE_LEVEL_ARM_V8_8_A — ARMv8.8-A
FEATURE_LEVEL_ARM_V8_9_A — ARMv8.9-A
FEATURE_LEVEL_ARM_V9_0_A — ARMv9.0-A
FEATURE_LEVEL_ARM_V9_1_A — ARMv9.1-A
FEATURE_LEVEL_ARM_V9_2_A — ARMv9.2-A
FEATURE_LEVEL_ARM_V9_3_A — ARMv9.3-A
FEATURE_LEVEL_ARM_V9_4_A — ARMv9.4-A
FEATURE_LEVEL_ARM_V9_5_A — ARMv9.5-A
NUM_FEATURE_LEVELS — valid feature level ids go 0..NUM_FEATURE_LEVELS - 1

🏷️ enum cpu_feature_t

CPU feature identifiers. and bestie, they gave us a whole usage example, so here's exactly how you'd use it:

...
struct cpu_raw_data_t raw;
struct cpu_id_t id;
if (cpuid_get_raw_data(&raw) == 0 && cpu_identify(&raw, &id) == 0) {
    if (id.flags[CPU_FEATURE_SSE2]) {
        // The CPU has SSE2...
        ...
    } else {
        // no SSE2
    }
} else {
  // processor cannot be determined.
}

and now, the full flag roster 🎀

CPU_FEATURE_FPU — Floating point unit
CPU_FEATURE_VME — Virtual mode extension
CPU_FEATURE_DE — Debugging extension
CPU_FEATURE_PSE — Page size extension
CPU_FEATURE_TSC — Time-stamp counter
CPU_FEATURE_MSR — Model-specific regsisters, RDMSR/WRMSR supported (yep, "regsisters" — we keep the typo, it's part of the lore now)
CPU_FEATURE_PAE — Physical address extension
CPU_FEATURE_MCE — Machine check exception
CPU_FEATURE_CX8 — CMPXCHG8B instruction supported
CPU_FEATURE_APIC — APIC support
CPU_FEATURE_MTRR — Memory type range registers
CPU_FEATURE_SEP — SYSENTER / SYSEXIT instructions supported
CPU_FEATURE_PGE — Page global enable
CPU_FEATURE_MCA — Machine check architecture
CPU_FEATURE_CMOV — CMOVxx instructions supported
CPU_FEATURE_PAT — Page attribute table
CPU_FEATURE_PSE36 — 36-bit page address extension
CPU_FEATURE_PN — Processor serial # implemented (Intel P3 only)
CPU_FEATURE_CLFLUSH — the CLFLUSH instruction is in the house ✨
CPU_FEATURE_DTS — debug store? supported 💖
CPU_FEATURE_ACPI — ACPI support, aka the power-states girlies 🎀
CPU_FEATURE_MMX — MMX instruction set, supported fr fr
CPU_FEATURE_FXSR — FXSAVE / FXRSTOR are supported, slay 💅
CPU_FEATURE_SSE — Streaming-SIMD Extensions (SSE), supported 🦋
CPU_FEATURE_SSE2 — SSE2 instructions, supported, no cap
CPU_FEATURE_SS — self-snoop, iconic
CPU_FEATURE_HT — hyper-threading is supported (tho it might be disabled, so don't come for me 😭)
CPU_FEATURE_TM — thermal monitor, keeping things chill 🌸
CPU_FEATURE_IA64 — IA64 supported (Itanium only, our niche queen 👑)
CPU_FEATURE_PBE — pending-break enable
CPU_FEATURE_PNI — PNI (SSE3) instructions, supported ✨
CPU_FEATURE_PCLMUL — the PCLMULQDQ instruction, supported 💜
CPU_FEATURE_DTS64 — 64-bit debug store, supported
CPU_FEATURE_MONITOR — MONITOR / MWAIT, supported 👑
CPU_FEATURE_DS_CPL — CPL qualified debug store
CPU_FEATURE_VMX — virtualization technology, supported 🔥
CPU_FEATURE_SMX — safer mode exceptions
CPU_FEATURE_EST — Enhanced SpeedStep
CPU_FEATURE_TM2 — thermal monitor 2, the sequel 💅
CPU_FEATURE_SSSE3 — SSSE3 instructions supported — and bestie, this is different from SSE3, do not confuse them, I'm begging 🙈
CPU_FEATURE_CID — context ID, supported
CPU_FEATURE_CX16 — the CMPXCHG16B instruction, supported ⭐
CPU_FEATURE_XTPR — send Task Priority Messages disable
CPU_FEATURE_PDCM — performance capabilities MSR, supported
CPU_FEATURE_DCA — direct cache access, supported 🦋
CPU_FEATURE_SSE4_1 — SSE 4.1 instructions, supported ✨
CPU_FEATURE_SSE4_2 — SSE 4.2 instructions, supported ✨
CPU_FEATURE_SYSCALL — SYSCALL / SYSRET instructions, supported 💖
CPU_FEATURE_XD — execute disable bit, supported
CPU_FEATURE_MOVBE — the MOVBE instruction, supported
CPU_FEATURE_POPCNT — the POPCNT instruction, supported, we love a count 🌈
CPU_FEATURE_AES — AES* instructions, supported 🔐✨
CPU_FEATURE_XSAVE — XSAVE/XRSTOR/etc instructions, supported 💜
CPU_FEATURE_OSXSAVE — a non-privileged copy of OSXSAVE, supported
CPU_FEATURE_AVX — advanced vector extensions, supported 🔥
CPU_FEATURE_MMXEXT — AMD MMX-extended instructions, supported 🎀
CPU_FEATURE_3DNOW — AMD 3DNow! instructions, supported (the exclamation mark is doing so much 💀)
CPU_FEATURE_3DNOWEXT — AMD 3DNow! extended instructions, supported
CPU_FEATURE_NX — no-execute bit, supported
CPU_FEATURE_FXSR_OPT — FFXSR: FXSAVE and FXRSTOR optimizations ✨
CPU_FEATURE_RDTSCP — the RDTSCP instruction, supported (AMD-only, exclusive behavior 💅)
CPU_FEATURE_LM — long mode (x86_64/EM64T), supported 👑
CPU_FEATURE_LAHF_LM — LAHF/SAHF supported in 64-bit mode
CPU_FEATURE_CMP_LEGACY — core multi-processing legacy mode
CPU_FEATURE_SVM — AMD Secure virtual machine 🔐
CPU_FEATURE_ABM — LZCNT instruction support
CPU_FEATURE_MISALIGNSSE — misaligned SSE, supported
CPU_FEATURE_SSE4A — SSE 4a, straight from AMD 💜
CPU_FEATURE_3DNOWPREFETCH — PREFETCH/PREFETCHW support, manifesting ahead of time ✨
CPU_FEATURE_OSVW — OS Visible Workaround (AMD)
CPU_FEATURE_IBS — instruction-based sampling
CPU_FEATURE_SSE5 — SSE 5 instructions supported — deprecated, and heads up, this will never be 1 💀 periodt
CPU_FEATURE_SKINIT — SKINIT / STGI, supported
CPU_FEATURE_WDT — watchdog timer support 🐶
CPU_FEATURE_TS — temperature sensor 🌡️
CPU_FEATURE_FID — frequency ID control
CPU_FEATURE_VID — voltage ID control
CPU_FEATURE_TTP — THERMTRIP
CPU_FEATURE_TM_AMD — AMD-specified hardware thermal control
CPU_FEATURE_STC — software thermal control
CPU_FEATURE_100MHZSTEPS — 100 MHz multiplier control
CPU_FEATURE_HWPSTATE — hardware P-state control 👑
CPU_FEATURE_CONSTANT_TSC — TSC ticks at a constant rate, steady as ever ✨
CPU_FEATURE_XOP — the XOP instruction set (it's the same as the old CPU_FEATURE_SSE5, glow-up era 💅)
CPU_FEATURE_FMA3 — the FMA3 instruction set
CPU_FEATURE_FMA4 — the FMA4 instruction set
CPU_FEATURE_TBM — trailing bit manipulation instruction support
CPU_FEATURE_F16C — 16-bit FP convert instruction support
CPU_FEATURE_RDRAND — the RdRand instruction 🎲
CPU_FEATURE_X2APIC — x2APIC, APIC_BASE.EXTD, MSRs 0000_0800h...0000_0BFFh 64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h) — also see standard level 0000_000Bh 📚
CPU_FEATURE_CPB — core performance boost 🚀
CPU_FEATURE_APERFMPERF — MPERF/APERF MSRs support
CPU_FEATURE_PFI — processor Feedback Interface support
CPU_FEATURE_PA — processor accumulator
CPU_FEATURE_AVX2 — AVX2 instructions 🔥
CPU_FEATURE_BMI1 — BMI1 instructions
CPU_FEATURE_BMI2 — BMI2 instructions
CPU_FEATURE_HLE — hardware Lock Elision prefixes
CPU_FEATURE_RTM — restricted Transactional Memory instructions
CPU_FEATURE_AVX512F — AVX-512 Foundation, the base of the 512 era 👑
CPU_FEATURE_AVX512DQ — AVX-512 Double/Quad granular insns
CPU_FEATURE_AVX512PF — AVX-512 Prefetch ✨
CPU_FEATURE_AVX512ER — AVX-512 Exponential/Reciprocal
CPU_FEATURE_AVX512CD — AVX-512 Conflict detection
CPU_FEATURE_SHA_NI — SHA-1/SHA-256 instructions 🔐
CPU_FEATURE_AVX512BW — AVX-512 Byte/Word granular insns
CPU_FEATURE_AVX512VL — AVX-512 128/256 vector length extensions
CPU_FEATURE_SGX — SGX extensions. Heads up: this one is non-autoritative (their spelling bestie, not mine 🙈) — go check cpu_id_t::sgx::present to verify presence, fr fr
CPU_FEATURE_RDSEED — the RDSEED instruction 🌱
CPU_FEATURE_ADX — ADX extensions (arbitrary precision)
CPU_FEATURE_AVX512VNNI — AVX-512 Vector Neural Network Instructions 🧠✨
CPU_FEATURE_AVX512VBMI — AVX-512 Vector Bit ManipulationInstructions (version 1) 💅
CPU_FEATURE_AVX512VBMI2 — AVX-512 Vector Bit ManipulationInstructions (version 2)
CPU_FEATURE_HYPERVISOR — hypervisor present (and it is always zero on physical CPUs, so if you see a 1, you're in someone's guest house 🏠)
CPU_FEATURE_SWAP — ARM: Swap instructions in the ARM instruction set
CPU_FEATURE_THUMB — ARM: Thumb instruction set support 👍
CPU_FEATURE_ADVMULTU — ARM: Advanced unsigned Multiply instructions
CPU_FEATURE_ADVMULTS — ARM: Advanced signed Multiply instructions
CPU_FEATURE_JAZELLE — ARM: Jazelle extension support ✨
CPU_FEATURE_DEBUGV6 — ARM: support for v6 Debug architecture
CPU_FEATURE_DEBUGV6P1 — ARM: support for v6.1 Debug architecture
CPU_FEATURE_THUMB2 — ARM: Thumb-2, instruction set support
CPU_FEATURE_DEBUGV7 — ARM: support for v7 Debug architecture
CPU_FEATURE_DEBUGV7P1 — ARM: support for v7.1 Debug architecture
CPU_FEATURE_THUMBEE — ARM: ThumbEE instruction set support
CPU_FEATURE_DIVIDE — ARM: Divide instructions ➗
CPU_FEATURE_LPAE — ARM: Large Physical Address Extension
CPU_FEATURE_PMUV1 — ARM: PMU extension version 1
CPU_FEATURE_PMUV2 — ARM: PMU extension version 2
CPU_FEATURE_ASID16 — ARM: 16 bit ASID
CPU_FEATURE_ADVSIMD — ARM: Advanced SIMD Extension
CPU_FEATURE_CRC32 — ARM: CRC32 instructions
CPU_FEATURE_CSV2_1P1 — ARM: Cache Speculation Variant 2
CPU_FEATURE_CSV2_1P2 — ARM: Cache Speculation Variant 2 version 1.2
CPU_FEATURE_CSV2_2 — ARM: Cache Speculation Variant 2 version 2
CPU_FEATURE_CSV2_3 — ARM: Cache Speculation Variant 2 version 3
CPU_FEATURE_DOUBLELOCK — ARM: Double Lock 🔒
CPU_FEATURE_ETS2 — ARM: Enhanced Translation Synchronization
CPU_FEATURE_FP — ARM: Floating Point extensions
CPU_FEATURE_MIXEDEND — ARM: Mixed-endian support
CPU_FEATURE_MIXEDENDEL0 — ARM: Mixed-endian support at EL0
CPU_FEATURE_PMULL — ARM: Advanced SIMD PMULL instructions
CPU_FEATURE_PMUV3 — ARM: PMU extension version 3
CPU_FEATURE_SHA1 — ARM: Advanced SIMD SHA1 instructions
CPU_FEATURE_SHA256 — ARM: Advanced SIMD SHA256 instructions
CPU_FEATURE_NTLBPA — ARM: Intermediate caching of translation table walks
CPU_FEATURE_HAFDBS — ARM: Hardware management of the Access flag and dirty state
CPU_FEATURE_HPDS — ARM: Hierarchical permission disables in translations tables
CPU_FEATURE_LOR — ARM: Limited ordering regions
CPU_FEATURE_LSE — ARM: Large System Extensions
CPU_FEATURE_PAN — ARM: Privileged access never
CPU_FEATURE_PMUV3P1 — ARM: Armv8.1 PMU extensions
CPU_FEATURE_RDM — ARM: Advanced SIMD rounding double multiply accumulate instructions
CPU_FEATURE_VHE — ARM: Virtualization Host Extensions
CPU_FEATURE_VMID16 — ARM: 16-bit VMID
CPU_FEATURE_AA32HPD — ARM: AArch32 Hierarchical permission disables
CPU_FEATURE_AA32I8MM — ARM: AArch32 Int8 matrix multiplication instructions
CPU_FEATURE_DPB — ARM: DC CVAP instruction
CPU_FEATURE_DEBUGV8P2 — ARM: Debug v8.2
CPU_FEATURE_F32MM — ARM: Single-precision Matrix Multiplication
CPU_FEATURE_F64MM — ARM: Double-precision Matrix Multiplication
CPU_FEATURE_FP16 — ARM: Half-precision floating-point data processing
CPU_FEATURE_HPDS2 — ARM: Hierarchical permission disables
CPU_FEATURE_I8MM — ARM: AArch64 Int8 matrix multiplication instructions
CPU_FEATURE_IESB — ARM: Implicit Error Synchronization event
CPU_FEATURE_LPA — ARM: Large PA and IPA support
CPU_FEATURE_LSMAOC — ARM: AArch32 Load/Store Multiple instruction atomicity and ordering controls
CPU_FEATURE_LVA — ARM: Large VA support
CPU_FEATURE_PAN2 — ARM: AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN
CPU_FEATURE_RAS — ARM: Reliability, Availability and Serviceability (RAS) Extension ✨
CPU_FEATURE_SHA3 — ARM: Advanced SIMD SHA3 instructions
CPU_FEATURE_SHA512 — ARM: Advanced SIMD SHA512 instructions
CPU_FEATURE_SM3 — ARM: Advanced SIMD SM3 instructions
CPU_FEATURE_SM4 — ARM: Advanced SIMD SM4 instructions
CPU_FEATURE_SPE — ARM: Statistical Profiling Extension
CPU_FEATURE_SVE — ARM: Scalable Vector Extension 👑

okay that's the whole flag lineup bestie, every last one of them, and yeah there are a LOT 💀 more coming in the next part, don't go anywhere 🫶

CPU_FEATURE_TTCNP — ARM: Translation table Common not private translations 💜
CPU_FEATURE_UAO — ARM: Unprivileged Access Override control
CPU_FEATURE_XNX — ARM: Translation table stage 2 Unprivileged Execute-never
CPU_FEATURE_CCIDX — ARM: Extended cache index 🎀
CPU_FEATURE_CONSTPACFIELD — ARM: PAC algorithm enhancement
CPU_FEATURE_EPAC — ARM: Enhanced pointer authentication
CPU_FEATURE_FCMA — ARM: Floating-point complex number instructions ✨
CPU_FEATURE_FPAC — ARM: Faulting on AUT* instructions
CPU_FEATURE_FPACCOMBINE — ARM: Faulting on combined pointer authentication instructions
CPU_FEATURE_JSCVT — ARM: JavaScript conversion instructions 🦋
CPU_FEATURE_LRCPC — ARM: Load-Acquire RCpc instructions
CPU_FEATURE_PACIMP — ARM: Pointer authentication - IMPLEMENTATION DEFINED algorithm
CPU_FEATURE_PACQARMA3 — ARM: Pointer authentication - QARMA3 algorithm
CPU_FEATURE_PACQARMA5 — ARM: Pointer authentication - QARMA5 algorithm
CPU_FEATURE_PAUTH — ARM: Pointer authentication 🔐
CPU_FEATURE_SPEV1P1 — ARM: Statistical Profiling Extension version 1
CPU_FEATURE_AMUV1 — ARM: Activity Monitors Extension version 1
CPU_FEATURE_BBM — ARM: Translation table break-before-make levels
CPU_FEATURE_DIT — ARM: Data Independent Timing instructions
CPU_FEATURE_DEBUGV8P4 — ARM: Debug v8.4
CPU_FEATURE_DOTPROD — ARM: Advanced SIMD dot product instructions 💅
CPU_FEATURE_DOUBLEFAULT — ARM: Double Fault Extension
CPU_FEATURE_FHM — ARM: Floating-point half-precision to single-precision multiply-add instructions
CPU_FEATURE_FLAGM — ARM: Condition flag manipulation instructions
CPU_FEATURE_IDST — ARM: ID space trap handling
CPU_FEATURE_LRCPC2 — ARM: Load-Acquire RCpc instructions version 2
CPU_FEATURE_LSE2 — ARM: Large System Extensions version 2
CPU_FEATURE_MPAM — ARM: Memory Partitioning and Monitoring Extension
CPU_FEATURE_PMUV3P4 — ARM: Arm8.4 PMU extensions
CPU_FEATURE_RASV1P1 — ARM: RAS extension v1.1
CPU_FEATURE_S2FWB — ARM: Stage 2 forced Write-Back
CPU_FEATURE_SEL2 — ARM: Secure EL2
CPU_FEATURE_TLBIOS — ARM: TLB invalidate instructions in Outer Shareable domain
CPU_FEATURE_TLBIRANGE — ARM: TLB invalidate range instructions
CPU_FEATURE_TRF — ARM: Self-hosted Trace extensions
CPU_FEATURE_TTL — ARM: Translation Table Level
CPU_FEATURE_TTST — ARM: Small translation tables
CPU_FEATURE_BTI — ARM: Branch Target Identification
CPU_FEATURE_CSV2 — ARM: Cache Speculation Variant 2
CPU_FEATURE_CSV3 — ARM: Cache Speculation Variant 3
CPU_FEATURE_DPB2 — ARM: DC CVADP instruction
CPU_FEATURE_E0PD — ARM: Preventing EL0 access to halves of address maps
CPU_FEATURE_EVT — ARM: Enhanced Virtualization Traps
CPU_FEATURE_EXS — ARM: Context synchronization and exception handling
CPU_FEATURE_FRINTTS — ARM: Floating-point to integer instructions
CPU_FEATURE_FLAGM2 — ARM: Enhancements to flag manipulation instructions
CPU_FEATURE_MTE — ARM: Memory Tagging Extension 🏷️
CPU_FEATURE_MTE2 — ARM: Memory Tagging Extension
CPU_FEATURE_PMUV3P5 — ARM: Arm8.5 PMU extensions
CPU_FEATURE_RNG — ARM: Random number generator 🎲
CPU_FEATURE_RNG_TRAP — ARM: Trapping support for RNDR/RNDRRS
CPU_FEATURE_SB — ARM: Speculation Barrier
CPU_FEATURE_SPECRES — ARM: Speculation restriction instructions
CPU_FEATURE_SSBS — ARM: Speculative Store Bypass Safe
CPU_FEATURE_SSBS2 — ARM: MRS and MSR instructions for SSBS version 2
CPU_FEATURE_AA32BF16 — ARM: AArch32 BFloat16 instructions
CPU_FEATURE_AMUV1P1 — ARM: Activity Monitors Extension version 1.1
CPU_FEATURE_BF16 — ARM: AArch64 BFloat16 instructions
CPU_FEATURE_DGH — ARM: Data Gathering Hint
CPU_FEATURE_ECV — ARM: Enhanced Counter Virtualization
CPU_FEATURE_FGT — ARM: Fine Grain Traps
CPU_FEATURE_HPMN0 — ARM: Setting of MDCR_EL2.HPMN to zero
CPU_FEATURE_MPAMV0P1 — ARM: Memory Partitioning and Monitoring extension version 0.1
CPU_FEATURE_MPAMV1P1 — ARM: Memory Partitioning and Monitoring extension version 1.1
CPU_FEATURE_MTPMU — ARM: Multi-threaded PMU extensions
CPU_FEATURE_PAUTH2 — ARM: Enhancements to pointer authentication
CPU_FEATURE_TWED — ARM: Delayed Trapping of WFE
CPU_FEATURE_AFP — ARM: Alternate floating-point behavior
CPU_FEATURE_EBF16 — ARM: AArch64 Extended BFloat16 behaviors
CPU_FEATURE_HCX — ARM: Support for the HCRX_EL2 register
CPU_FEATURE_LPA2 — ARM: Larger physical address for 4KB and 16KB translation granules
CPU_FEATURE_LS64 — ARM: Support for 64-byte loads and stores without status
CPU_FEATURE_LS64_ACCDATA — ARM: Support for 64-byte EL0 stores with status
CPU_FEATURE_LS64_V — ARM: Support for 64-byte stores with status
CPU_FEATURE_MTE3 — ARM: MTE Asymmetric Fault Handling
CPU_FEATURE_MTE_ASYM_FAULT — ARM: Memory tagging asymmetric faults
CPU_FEATURE_PAN3 — ARM: Support for SCTLR_ELx.EPAN
CPU_FEATURE_PMUV3P7 — ARM: Armv8.7 PMU extensions
CPU_FEATURE_RPRES — ARM: Increased precision of FRECPE and FRSQRTE
CPU_FEATURE_SPEV1P2 — ARM: Statistical Profiling Extensions version 1.2
CPU_FEATURE_WFXT — ARM: WFE and WFI instructions with timeout ⏰
CPU_FEATURE_XS — ARM: XS attribute
CPU_FEATURE_CMOW — ARM: Control for cache maintenance permission
CPU_FEATURE_DEBUGV8P8 — ARM: Debug v8.8
CPU_FEATURE_HBC — ARM: Hinted conditional branches
CPU_FEATURE_MOPS — ARM: Standardization of memory operations
CPU_FEATURE_NMI — ARM: Non-maskable Interrupts
CPU_FEATURE_PMUV3P8 — ARM: Armv8.8 PMU extensions
CPU_FEATURE_SCTLR2 — ARM: Extension to SCTLR_ELx
CPU_FEATURE_SPEV1P3 — ARM: Statistical Profiling Extensions version 1.3
CPU_FEATURE_TCR2 — ARM: Support for TCR2_ELx
CPU_FEATURE_TIDCP1 — ARM: EL0 use of IMPLEMENTATION DEFINED functionality
CPU_FEATURE_ADERR — ARM: Asynchronous Device Error Exceptions
CPU_FEATURE_AIE — ARM: Memory Attribute Index Enhancement
CPU_FEATURE_ANERR — ARM: Asynchronous Normal Error Exceptions
CPU_FEATURE_ATS1A — ARM: Address Translation operations that ignore stage 1 permissions
CPU_FEATURE_CLRBHB — ARM: Support for Clear Branch History instruction
CPU_FEATURE_CSSC — ARM: Common Short Sequence Compression instructions 🗜️
CPU_FEATURE_DEBUGV8P9 — ARM: Debug v8.9
CPU_FEATURE_DOUBLEFAULT2 — ARM: Double Fault Extension v2
CPU_FEATURE_ECBHB — ARM: Exploitative control using branch history information
CPU_FEATURE_FGT2 — ARM: Fine-grained traps 2
CPU_FEATURE_HAFT — ARM: Hardware managed Access Flag for Table descriptors
CPU_FEATURE_LRCPC3 — ARM: Load-Acquire RCpc instructions version 3
CPU_FEATURE_MTE4 — ARM: Enhanced Memory Tagging Extension
CPU_FEATURE_MTE_ASYNC — ARM: Asynchronous reporting of Tag Check Fault
CPU_FEATURE_MTE_CANONICAL_TAGS — ARM: Canonical Tag checking for Untagged memory
CPU_FEATURE_MTE_NO_ADDRESS_TAGS — ARM: Memory tagging with Address tagging disabled
CPU_FEATURE_MTE_PERM — ARM: Allocation tag access permission
CPU_FEATURE_MTE_STORE_ONLY — ARM: Store-only Tag Checking
CPU_FEATURE_MTE_TAGGED_FAR — ARM: FAR_ELx on a Tag Check Fault
CPU_FEATURE_PFAR — ARM: Physical Fault Address Register Extension
CPU_FEATURE_PMUV3_ICNTR — ARM: Fixed-function instruction counter
CPU_FEATURE_PMUV3_SS — ARM: PMU Snapshot extension
CPU_FEATURE_PMUV3P9 — ARM: Armv8.9 PMU extensions
CPU_FEATURE_PRFMSLC — ARM: SLC target support for PRFM instructions
CPU_FEATURE_RASV2 — ARM: RAS Extension v2
CPU_FEATURE_RPRFM — ARM: Support for Range Prefetch Memory instruction
CPU_FEATURE_S1PIE — ARM: Stage 1 permission indirections
CPU_FEATURE_S1POE — ARM: Stage 1 permission overlays
CPU_FEATURE_S2PIE — ARM: Stage 2 permission indirections
CPU_FEATURE_S2POE — ARM: Stage 2 permission overlays
CPU_FEATURE_SPECRES2 — ARM: Enhanced speculation restriction instructions
CPU_FEATURE_SPE_DPFZS — ARM: Disable Cycle Counter on SPE Freeze
CPU_FEATURE_SPEV1P4 — ARM: Statistical Profiling Extension version 1.4
CPU_FEATURE_SPMU — ARM: System Performance Monitors Extension
CPU_FEATURE_THE — ARM: Translation Hardening Extension
CPU_FEATURE_SVE2 — ARM: Scalable Vector Extension version 2 🌈
CPU_FEATURE_SVE_AES — ARM: Scalable Vector AES instructions
CPU_FEATURE_SVE_BITPERM — ARM: Scalable Vector Bit Permutes instructions
CPU_FEATURE_SVE_PMULL128 — ARM: SVE single-vector Advanced Encryption Standard and 128-bit polynomial multiply long instructions
CPU_FEATURE_SVE_SHA3 — ARM: Scalable Vector SHA3 instructions
CPU_FEATURE_SVE_SM4 — ARM: Scalable Vector SM4 instructions
CPU_FEATURE_TME — ARM: Transactional Memory Extension
CPU_FEATURE_TRBE — ARM: Trace Buffer Extension
CPU_FEATURE_BRBE — ARM: Branch Record Buffer Extension
CPU_FEATURE_RME — ARM: Realm Management Extension
CPU_FEATURE_SME — ARM: Scalable Matrix Extension
CPU_FEATURE_SME_F64F64 — ARM: Double-precision floating-point outer product instructions
CPU_FEATURE_SME_FA64 — ARM: Full A64 instruction set support in Streaming SVE mode
CPU_FEATURE_SME_I16I64 — ARM: 16-bit to 64-bit integer widening outer product instructions
CPU_FEATURE_BRBEV1P1 — ARM: Branch Record Buffer Extension version 1.1
CPU_FEATURE_MEC — ARM: Memory Encryption Contexts
CPU_FEATURE_SME2 — ARM: Scalable Matrix Extensions version 2
CPU_FEATURE_ABLE — ARM: Address Breakpoint Linking Extension
CPU_FEATURE_BWE — ARM: Breakpoint and watchpoint enhancements 👑
CPU_FEATURE_D128 — ARM: 128-bit Translation Tables, 56 bit PA
CPU_FEATURE_EBEP — ARM: Exception-based Event Profiling
CPU_FEATURE_GCS — ARM: Guarded Control Stack Extension
CPU_FEATURE_ITE — ARM: Instrumentation Trace Extension
CPU_FEATURE_LSE128 — ARM: 128-bit Atomics
CPU_FEATURE_LVA3 — ARM: 56-bit VA
CPU_FEATURE_SEBEP — ARM: Synchronous Exception-based Event Profiling
CPU_FEATURE_SME2P1 — ARM: Scalable Matrix Extension version 2.1
CPU_FEATURE_SME_F16F16 — ARM: Non-widening half-precision FP16 to FP16 arithmetic for SME2
CPU_FEATURE_SVE2P1 — ARM: Scalable Vector Extensions version 2.1
CPU_FEATURE_SVE_B16B16 — ARM: Non-widening BFloat16 to BFloat16 arithmetic for SVE2 and SME2
CPU_FEATURE_SYSINSTR128 — ARM: 128-bit System instructions
CPU_FEATURE_SYSREG128 — ARM: 128-bit System registers
CPU_FEATURE_TRBE_EXT — ARM: Trace Buffer external mode
CPU_FEATURE_ASID2 — ARM: Support for concurrent use of two ASIDs
CPU_FEATURE_BWE2 — ARM: Breakpoint and watchpoint enhancements 2
CPU_FEATURE_CPA — ARM: Instruction-only Checked Pointer Arithmetic
CPU_FEATURE_CPA2 — ARM: Checked Pointer Arithmetic
CPU_FEATURE_E2H0 — ARM: Programming of HCR_EL2.E2H.
CPU_FEATURE_E3DSE — ARM: Delegated SError exception injection
CPU_FEATURE_ETS3 — ARM: Enhanced Translation Synchronization
CPU_FEATURE_FAMINMAX — ARM: Floating-point maximum and minimum absolute value instructions
CPU_FEATURE_FGWTE3 — ARM: Fine-Grained Write Trap EL3
CPU_FEATURE_FP8 — ARM: FP8 convert instructions
CPU_FEATURE_FP8DOT2 — ARM: FP8 2-way dot product to half-precision instructions
CPU_FEATURE_FP8DOT4 — ARM: FP8 4-way dot product to single-precision instructions
CPU_FEATURE_FP8FMA — ARM: FP8 multiply-accumulate to half-precision and single-precision instructions
CPU_FEATURE_FPMR — ARM: Floating-point Mode Register
CPU_FEATURE_HACDBS — ARM: Hardware accelerator for cleaning Dirty state
CPU_FEATURE_HDBSS — ARM: Hardware Dirty state tracking structure
CPU_FEATURE_LUT — ARM: Lookup table instructions with 2-bit and 4-bit indices
CPU_FEATURE_PAUTH_LR — ARM: Pointer authentication instructions that allow signing of LR using SP and PC as diversifiers
CPU_FEATURE_RME_GPC2 — ARM: RME Granule Protection Check 2 Extension
CPU_FEATURE_SME_F8F16 — ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to half-precision instructions
CPU_FEATURE_SME_F8F32 — ARM: SME2 ZA-targeting FP8 multiply-accumulate, dot product, and outer product to single-precision instructions
CPU_FEATURE_SME_LUTV2 — ARM: Lookup table instructions with 4-bit indices and 8-bit elements
CPU_FEATURE_SPMU2 — ARM: System Performance Monitors Extension version 2
CPU_FEATURE_SSVE_FP8DOT2 — ARM: SVE FP8 2-way dot product to half-precision instructions in Streaming SVE mode
CPU_FEATURE_SSVE_FP8DOT4 — ARM: SVE2 FP8 4-way dot product to single-precision instructions in Streaming SVE mode
CPU_FEATURE_SSVE_FP8FMA — ARM: SVE2 FP8 multiply-accumulate to half-precision and single-precision instructions in Streaming SVE mode
CPU_FEATURE_STEP2 — ARM: Enhanced Software Step Extension
CPU_FEATURE_TLBIW — ARM: TLBI VMALL for Dirty state

🌸 enum cpu_hint_t 🌸

CPU detection hints identifiers. Usage: similar to the flags usage

Enumerator

CPU_HINT_SSE_SIZE_AUTH — SSE unit size is authoritative (not only a Family/Model guesswork, but based on an actual CPUID bit)

💅 enum cpu_msrinfo_request_t 💅

Enumerator

INFO_MPERF — Maximum performance frequency clock. This is a counter, which increments as a proportion of the actual processor speed.
INFO_APERF — Actual performance frequency clock. This accumulates the core clock counts when the core is active.
INFO_MIN_MULTIPLIER — Minimum CPU:FSB ratio for this CPU, multiplied by 100.
INFO_CUR_MULTIPLIER — Current CPU:FSB ratio, multiplied by 100. e.g., a CPU:FSB value of 18.5 reads as "1850".
INFO_MAX_MULTIPLIER — Maximum CPU:FSB ratio for this CPU, multiplied by 100.
INFO_TEMPERATURE — The current core temperature in Celsius.
INFO_THROTTLING — 1 if the current logical processor is throttling. 0 if it is running normally.
INFO_VOLTAGE — The current core voltage in Volt, multiplied by 100.
INFO_BCLK — See INFO_BUS_CLOCK.
INFO_BUS_CLOCK — The main bus clock in MHz, e.g., FSB/QPI/DMI/HT base clock, multiplied by 100.

🦋 enum cpu_purpose_t 🦋

CPU purpose.

Enumerator

PURPOSE_GENERAL — general purpose CPU
PURPOSE_PERFORMANCE — performance CPU
PURPOSE_EFFICIENCY — efficiency CPU
PURPOSE_LP_EFFICIENCY — low-power efficiency CPU
PURPOSE_U_PERFORMANCE — ultimate performance CPU
NUM_CPU_PURPOSES — Valid CPU purpose ids: 0..NUM_CPU_PURPOSES - 1

🎀 enum cpu_sgx_feature_t 🎀

SGX features flags.

See also

cpu_sgx_t

Usage:

...
struct cpu_raw_data_t raw;
struct cpu_id_t id;
if (cpuid_get_raw_data(&raw) == 0 && cpu_identify(&raw, &id) == 0 && id.sgx.present) {
    if (id.sgx.flags[INTEL_SGX1])
        // The CPU has SGX1 instructions support...
        ...
    } else {
        // no SGX
    }
} else {
  // processor cannot be determined.
}

Enumerator

INTEL_SGX1 — SGX1 instructions support
INTEL_SGX2 — SGX2 instructions support

🔥 enum cpu_vendor_t 🔥

CPU vendor, as guessed from the Vendor String.

Enumerator

VENDOR_INTEL — Intel CPU
VENDOR_AMD — AMD CPU
VENDOR_CYRIX — Cyrix CPU
VENDOR_NEXGEN — NexGen CPU
VENDOR_TRANSMETA — Transmeta CPU
VENDOR_UMC — x86 CPU by UMC
VENDOR_CENTAUR — x86 CPU by IDT
VENDOR_RISE — x86 CPU by Rise Technology
VENDOR_SIS — x86 CPU by SiS
VENDOR_NSC — x86 CPU by National Semiconductor
VENDOR_HYGON — Hygon CPU
VENDOR_ARM — ARM CPU
VENDOR_BROADCOM — Broadcom Corporation CPU
VENDOR_CAVIUM — Cavium Inc. CPU
VENDOR_DEC — Digital Equipment Corporation CPU
VENDOR_FUJITSU — Fujitsu Ltd. CPU
VENDOR_HISILICON — HiSilicon Technology Co., Ltd. CPU
VENDOR_INFINEON — Infineon Technologies AG CPU
VENDOR_FREESCALE — Motorola or Freescale Semiconductor Inc. CPU
VENDOR_NVIDIA — NVIDIA Corporation CPU
VENDOR_APM — Applied Micro Circuits Corporation CPU
VENDOR_QUALCOMM — Qualcomm Inc. CPU
VENDOR_SAMSUNG — Samsung Group CPU
VENDOR_MARVELL — Marvell International Ltd. CPU
VENDOR_APPLE — Apple Inc. CPU
VENDOR_FARADAY — Faraday Technology CPU
VENDOR_MICROSOFT — Microsoft Corporation CPU
VENDOR_PHYTIUM — Phytium Technology Co., Ltd CPU
VENDOR_AMPERE — Ampere Computing CPU
NUM_CPU_VENDORS — Valid CPU vendor ids: 0..NUM_CPU_VENDORS - 1

💜 enum hypervisor_vendor_t 💜

Hypervisor vendor, as guessed from the CPU_FEATURE_HYPERVISOR flag.

Enumerator

HYPERVISOR_NONE — no hypervisor
HYPERVISOR_BHYVE — FreeBSD bhyve hypervisor
HYPERVISOR_HYPERV — Microsoft Hyper-V or Windows Virtual PC hypervisor
HYPERVISOR_KVM — KVM hypervisor
HYPERVISOR_PARALLELS — Parallels hypervisor
HYPERVISOR_QEMU — QEMU hypervisor
HYPERVISOR_VIRTUALBOX — VirtualBox hypervisor
HYPERVISOR_VMWARE — VMware hypervisor
HYPERVISOR_XEN — Xen hypervisor
NUM_HYPERVISOR_VENDORS — Valid hypervisor vendor ids: 0..NUM_HYPERVISOR_VENDORS - 1

✨ Function Documentation ✨

🌈 `char * affinity_mask_str (cpu_affinity_mask_t * affinity_mask)` 🌈

Returns textual representation of a CPU affinity mask.

Parameters

affinity_mask — the affinity mask (in hexadecimal), whose textual representation is wanted.

Note

This function is not thread-safe 💀

Returns

a string like "0000FFFF", "00FF0000", etc.

🧚 `char * affinity_mask_str_r (cpu_affinity_mask_t * affinity_mask, char * buffer, uint32_t buffer_len)` 🧚

Returns textual representation of a CPU affinity mask (thread-safe)

Parameters

affinity_mask — Input — the affinity mask (in hexadecimal), whose textual representation is wanted.
buffer — Output — an allocated string where to store the textual representation, like "0000FFFF", "00FF0000", etc.
buffer_len — Input — the size of buffer.

Returns

a pointer on buffer

🍓 `const char * cpu_architecture_str (cpu_architecture_t architecture)` 🍓

Returns the short textual representation of a CPU architecture.

Parameters

architecture — the architecture, whose textual representation is wanted.

Returns

a constant string like "x86", "ARM", etc.

👑 `int cpu_clock (void )` 👑

Get the CPU clock frequency (all-in-one method). This is an all-in-one method for getting the CPU clock frequency. It tries to use the OS for that. If the OS doesn't have this info, it uses cpu_clock_measure with 200ms time interval and quadruple checking.

Returns

the CPU clock frequency in MHz. If every possible method fails, the result is -1.

🔥 `int cpu_clock_by_ic (int millis, int runs)` 🔥

Measure the CPU clock frequency using instruction-counting.

Parameters

millis — how much time to allocate for each run, in milliseconds
runs — how many runs to perform

The function performs a busy-wait cycle using a known number of "heavy" (SSE) instructions. These instructions run at (more or less guaranteed) 1 IPC rate, so by running a busy loop for a fixed amount of time, and measuring the amount of instructions done, the CPU clock is accurately measured.

Of course, this function is still affected by the power-saving schemes, so the warnings as of cpu_clock_measure() still apply. However, this function is immune to problems with detection, related to the Intel Nehalem's "Turbo" mode, where the internal clock is raised, but the RDTSC rate is unaffected.

The function will run for about (millis * runs) milliseconds. You can make just a single busy-wait run (runs == 1), but bestie… task scheduling can show up uninvited and absolutely wreck your counting, so allowing more than one run is the recommended move. And since run length isn't imperative for accurate readings (like, 50ms is genuinely enough), you can totally afford a bunch of short runs — e.g. 10 runs of 50ms, or 20 runs of 25ms. ✨

Recommended values — millis = 50, runs = 4. Want more robustness? Just bump up the number of runs. 💅

NOTE: on Bulldozer and later CPUs, the busy-wait cycle runs at 1.4 IPC, so the results get skewed. This is corrected internally by dividing the resulting value by 1.4. BUT — this only happens if the thread is executed on a single CMT module. If there are other threads competing for resources, the results are unpredictable. Make sure you run cpu_clock_by_ic() on a CPU that is free from competing threads, or if there are such threads, they shouldn't exceed the number of modules. On a Bulldozer X8, that means 4 threads. 🧚

Returns — the CPU clock frequency in MHz (within some measurement error margin). If SSE is not supported, the result is -1. If the input parameters are incorrect, or some other internal fault is detected, the result is -2.

`int cpu_clock_by_mark (struct cpu_mark_t * mark)`

Calculates the CPU clock. 👑

Parameters

mark — pointer to a cpu_mark_t structure, which has been initialized with cpu_tsc_mark and later stopped with cpu_tsc_unmark.

Note

For reliable results, the marked time interval should be at least about 10 ms. ⏱️

Returns — the CPU clock frequency, in MHz. Due to measurement error, it will differ from the true value in a few least-significant bits. Accuracy depends on the timing interval — the more, the better. If the timing interval is insufficient, the result is -1. Also, see the comment on cpu_clock_measure for additional issues and pitfalls in using RDTSC for CPU frequency measurements. 🫶

`int cpu_clock_by_os (void )`

Returns the CPU clock, as reported by the OS. This function uses OS-specific functions to obtain the CPU clock. It may differ from the true clock for several reasons:

i) The CPU might be in some power saving state, while the OS reports its full-power frequency, or vice-versa.
ii) In some cases you can raise or lower the CPU frequency with overclocking utilities and the OS will not notice. 😭

Returns — the CPU clock frequency in MHz. If the OS is not (yet) supported or lacks the necessary reporting machinery, the return value is -1.

`int cpu_clock_by_tsc (struct cpu_raw_data_t * raw)`

Measure the CPU clock frequency using TSC frequency from CPUID. 🌈

Parameters

raw — Optional input — a pointer to the raw CPUID data, which is obtained either by cpuid_get_raw_data or cpuid_deserialize_raw_data. Can also be NULL, in which case the functions calls cpuid_get_raw_data itself.

The function read Time Stamp Counter and Nominal Core Crystal Clock Information Leaf from CPUID. It determines the processor base frequency. 🔥

NOTE: only x86 Intel CPUs since Skylake (6th generation of Intel Core processors) are supported. Other vendors do not support this feature. no cap, that's the whole list

Returns — the CPU clock frequency in MHz. If TSC frequency is not supported, the result is -1. If the input parameters are incorrect, or some other internal fault is detected, the result is -2.

`int cpu_clock_measure (int millis, int quad_check)`

Measure the CPU clock frequency. ✨

Parameters

millis — How much time to waste in the busy-wait cycle. In millisecs. Useful values 10 - 1000
quad_check — Do a more thorough measurement if nonzero (see the explanation).

The function performs a busy-wait cycle for the given time and calculates the CPU frequency by the difference of the TSC values. The accuracy of the calculation depends on the length of the busy-wait cycle: more is better, but 100ms should be enough for most purposes.

While this will calculate the CPU frequency correctly in most cases, there are several reasons why it might be incorrect:

i) RDTSC doesn't guarantee it will run at the same clock as the CPU. Apparently there aren't CPUs at the moment, but still, there's no guarantee.
ii) The CPU might be in a low-frequency power saving mode, and the CPU might be switched to higher frequency at any time. If this happens during the measurement, the result can be anywhere between the low and high frequencies. Also, if you're interested in the high frequency value only, this function might return the low one instead.
iii) On SMP systems exhibiting TSC drift (see cpu_rdtsc)

the quad_check option will run four consecutive measurements and then return the average of the two most-consistent results. The total runtime of the function will still be millis — consider using a bit more time for the timing interval.

Finally, for benchmarking / CPU intensive applications, the best strategy is to use the cpu_tsc_mark() / cpu_tsc_unmark() / cpu_clock_by_mark() method. Begin by mark()-ing about one second after application startup (allowing the power-saving manager to kick in and rise the frequency during that time), then unmark() just before application finishing. The result will most acurately represent at what frequency your app was running. 💯

Returns — the CPU clock frequency in MHz (within some measurement error margin). If RDTSC is not supported, the result is -1.

`void cpu_exec_cpuid (uint32_t eax, uint32_t * regs)`

Executes the CPUID instruction. 🎀

Parameters

eax — the value of the EAX register when executing CPUID
regs — the results will be stored here. regs[0] = EAX, regs[1] = EBX, ...

Note

CPUID will be executed with EAX set to the given value and EBX, ECX, EDX set to zero.

`void cpu_exec_cpuid_ext (uint32_t * regs)`

Executes the CPUID instruction with the given input registers. 🦋

Note

This is just a bit more generic version of cpu_exec_cpuid — it allows you to control all the registers.

Parameters

regs — Input/output. Prior to executing CPUID, EAX, EBX, ECX and EDX will be set to regs[0], regs[1], regs[2] and regs[3]. After CPUID, this array will contain the results.

`const char * cpu_feature_level_str (cpu_feature_level_t level)`

Returns the short textual representation of a CPU feature level. 🌸

Parameters

level — the feature level, whose textual representation is wanted.

Returns — a constant string like "ARMv8.0-A", "ARMv9.4-A", etc.

`const char * cpu_feature_str (cpu_feature_t feature)`

Returns the short textual representation of a CPU flag. ⭐

Parameters

feature — the feature, whose textual representation is wanted.

Returns — a constant string like "fpu", "tsc", "sse2", etc.

Note

the names of the returned flags are compatible with those from /proc/cpuinfo in Linux, with the exception of tm_amd 💅

`int cpu_identify (struct cpu_raw_data_t * raw, struct cpu_id_t * data)`

Identifies the CPU. 👑

Parameters

raw — Input — a pointer to the raw CPUID data, which is obtained either by cpuid_get_raw_data or cpuid_deserialize_raw_data. Can also be NULL, in which case the functions calls cpuid_get_raw_data itself.
data — Output — the decoded CPU features/info is written here.

Note

The function will not fail, even if some of the information cannot be obtained. Even when the CPU is new and thus unknown to libcpuid, some generic info, such as "AMD K9 family CPU" will be written to data.cpu_codename, and most other things, such as the CPU flags, cache sizes, etc. should be detected correctly anyway. However, the function CAN fail, if the CPU is completely alien to libcpuid. 💀

While cpu_identify() and cpuid_get_raw_data() are fast for most purposes, running them several thousand times per second can hamper performance significantly. Specifically, avoid writing "cpu feature checker" wrapping function, which calls cpu_identify and returns the value of some flag, if that function is going to be called frequently. 🙈

Returns — zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`int cpu_identify_all (struct cpu_raw_data_array_t * raw_array, struct system_id_t * system)`

Identifies all the CPUs. 🌈

Parameters

raw_array — Input — a pointer to the array of raw CPUID data, which is obtained either by cpuid_get_all_raw_data or cpuid_deserialize_all_raw_data. Can also be NULL, in which case the functions calls cpuid_get_all_raw_data itself.
system — Output — the decoded CPU features/info is written here for each CPU type.

Note

The function is similar to cpu_identify. Refer to cpu_identify notes.

As the memory is dynamically allocated, be sure to call cpuid_free_raw_data_array() and cpuid_free_system_id() after you're done with the data 🫶

Returns — zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`int cpu_msr_driver_close (struct msr_driver_t * handle)`

Closes an open MSR driver. This function unloads the MSR driver opened by cpu_msr_driver_open and frees any resources associated with it. 🧚

Parameters

handle — a handle to the MSR reader driver, as created by cpu_msr_driver_open

Returns — zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`struct msr_driver_t * cpu_msr_driver_open (void )`

Starts/opens a driver, needed to read MSRs (Model Specific Registers). On systems that support it, this function will create a temporary system driver, that has privileges to execute the RDMSR instruction. After the driver is created, you can read MSRs by calling cpu_rdmsr 🔥

Returns — a handle to the driver on success, and NULL on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`struct msr_driver_t * cpu_msr_driver_open_core (unsigned core_num)`

Similar to cpu_msr_driver_open, but accept one parameter. This function works on certain operating systems (GNU/Linux, FreeBSD) 💅

Parameters

core_num specify the core number for MSR. The first core number is 0. The last core number is cpuid_get_total_cpus - 1.

Returns — a handle to the driver on success, and NULL on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`int cpu_msrinfo (struct msr_driver_t * handle, cpu_msrinfo_request_t which)`

okay bestie, this one reads extended CPU info straight outta the Model-Specific Registers ✨

Parameters

handle — a handle to an open MSR driver,

Parameters

which — which info field should be returned. A list of available information entities is listed in the cpu_msrinfo_request_t enum.

Return values

if the requested information is available for the current processor model, the respective value is returned. if no information is available, or the CPU doesn't support the query, the special value CPU_INVALID_VALUE is returned

Note

This function is not MT-safe. If you intend to call it from multiple threads, guard it through a mutex or a similar primitive. 🫶

`const char * cpu_purpose_str (cpu_purpose_t purpose)`

Gives you the short textual glow-up of a CPU purpose 💅

Parameters

purpose — the purpose, whose textual representation is wanted.

Returns

a constant string like "general", "performance", "efficiency", etc. 🎀

`int cpu_rdmsr (struct msr_driver_t * handle, uint32_t msr_index, uint64_t * result)`

Reads a Model-Specific Register (MSR) 💖 If the CPU has MSRs (as indicated by the CPU_FEATURE_MSR flag), you can read a MSR with the given index by calling this function.

There are several prerequisites you must do before reading MSRs: 1) You must ensure the CPU has RDMSR. Check the CPU_FEATURE_MSR flag in cpu_id_t::flags 2) You must ensure that the CPU implements the specific MSR you intend to read. 3) You must open a MSR-reader driver. RDMSR is a privileged instruction and needs ring-0 access in order to work. This temporary driver is created by calling cpu_msr_driver_open

Parameters

handle — a handle to the MSR reader driver, as created by cpu_msr_driver_open
msr_index — the numeric ID of the MSR you want to read
result — a pointer to a 64-bit integer, where the MSR value is stored

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

`int cpu_rdmsr_range (struct msr_driver_t * handle, uint32_t msr_index, uint8_t highbit, uint8_t lowbit, uint64_t * result)`

Same energy as cpu_rdmsr, but it extracts a range of bits 🦋

Parameters

handle — a handle to the MSR reader driver, as created by cpu_msr_driver_open
msr_index — the numeric ID of the MSR you want to read
highbit — the high bit in range, must be inferior to 64
lowbit — the low bit in range, must be equal or superior to 0
result — a pointer to a 64-bit integer, where the MSR value is stored

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

`void cpu_rdtsc (uint64_t * result)`

Executes RDTSC ✨ The RDTSC (ReaD Time Stamp Counter) instruction gives access to an internal 64-bit counter, which usually increments at each clock cycle. This can be used for various timing routines, and as a very precise clock source. It is set to zero on system startup. Beware that may not increment at the same frequency as the CPU. Consecutive calls of RDTSC are, however, guaranteed to return monotonically-increasing values. 👑

Parameters

result — a pointer to a 64-bit unsigned integer, where the TSC value will be stored

Note

If 100% compatibility is a concern, you must first check if the RDTSC instruction is present (if it is not, your program will crash with "invalid opcode" exception). Only some very old processors (i486, early AMD K5 and some Cyrix CPUs) lack that instruction — they should have become exceedingly rare these days. To verify RDTSC presence, run cpu_identify() and check flags[CPU_FEATURE_TSC]. 😭

The monotonically increasing nature of the TSC may be violated on SMP systems, if their TSC clocks run at different rate. If the OS doesn't account for that, the TSC drift may become arbitrary large. 💀

`int cpu_request_core_type (cpu_purpose_t purpose, struct cpu_raw_data_array_t * raw_array, struct cpu_id_t * data)`

Identifies a given CPU type 🌸

Parameters

purpose — Input - a cpu_purpose_t to request
raw_array — Optional input - a pointer to the array of raw CPUID data, which is obtained either by cpuid_get_all_raw_data or cpuid_deserialize_all_raw_data. Can also be NULL, in which case the functions calls cpuid_get_all_raw_data itself.
data — Output - the decoded CPU features/info is written here.

Returns

zero if successful, and some negative number on error (like ERR_NOT_FOUND if CPU type not found). The error message can be obtained by calling cpuid_error.

`void cpu_tsc_mark (struct cpu_mark_t * mark)`

Store TSC and timing info 🎀 This function stores the current TSC value and current time info from a precise OS-specific clock source in the cpu_mark_t structure. The sys_clock field contains time with microsecond resolution. The values can later be used to measure time intervals, number of clocks, FPU frequency, etc. ✨

Parameters

mark [out] — a pointer to a cpu_mark_t structure

`void cpu_tsc_unmark (struct cpu_mark_t * mark)`

Calculate TSC and timing difference 🦋

Parameters

mark — input/output: a pointer to a cpu_mark_t structure, which has already been initialized by cpu_tsc_mark. The difference in TSC and time will be written here.

This function calculates the TSC and time difference, by obtaining the current TSC and timing values and subtracting the contents of the mark structure from them. Results are written in the same structure. 💖

Example:

...
struct cpu_mark_t mark;
cpu_tsc_mark(&mark);
foo();
cpu_tsc_unmark(&mark);
printf("Foo finished. Executed in %llu cycles and %llu usecs\n",
       mark.tsc, mark.sys_clock);
...

`int cpuid_deserialize_all_raw_data (struct cpu_raw_data_array_t * data, const char * filename)`

Reads all raw CPUID data from file 🌈

Parameters

data — a pointer to cpu_raw_data_array_t structure. The deserialized array data will be written here.
filename — the path of the file, containing the serialized raw data. If empty, stdin will be used.

Note

This function may fail, if the file is created by different version of the library. Also, see the notes on cpuid_serialize_all_raw_data. 🙈

As the memory is dynamically allocated, be sure to call cpuid_free_raw_data_array() after you're done with the data ⭐

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

`int cpuid_deserialize_raw_data (struct cpu_raw_data_t * data, const char * filename)`

Reads raw CPUID data from file 💜

Parameters

data — a pointer to cpu_raw_data_t structure. The deserialized data will be written here.
filename — the path of the file, containing the serialized raw data. If empty, stdin will be used.

Note

This function may fail, if the file is created by different version of the library. Also, see the notes on cpuid_serialize_raw_data. 💀

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

`const char * cpuid_error (void )`

Returns textual description of the last error 🫶 libcpuid stores an errno-style error status, whose description can be obtained with this function.

Note

This function is not thread-safe 😭

`void cpuid_free_cpu_list (struct cpu_list_t * list)`

Frees a CPU list 🧚 This function deletes all the memory associated with a CPU list, as obtained by cpuid_get_cpu_list()

Parameters

list — the list to be free()'d.

`void cpuid_free_raw_data_array (struct cpu_raw_data_array_t * raw_array)`

Frees a raw array ✨ This function deletes all the memory associated with a raw array, as obtained by cpuid_get_all_raw_data(), cpuid_deserialize_all_raw_data() and cpu_identify_all()

Parameters

raw_array — the raw array to be free()'d.

`void cpuid_free_system_id (struct system_id_t * system)`

Frees a system ID type 💅 This function deletes all the memory associated with a system ID, as obtained by cpu_identify_all()

Parameters

system — the system ID to be free()'d.

`int cpuid_get_all_raw_data (struct cpu_raw_data_array_t * data)`

Obtains the raw CPUID data from all CPUs 🌸

Parameters

data — a pointer to cpu_raw_data_array_t structure

Note

As the memory is dynamically allocated, be sure to call cpuid_free_raw_data_array() after you're done with the data 🎀

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

`void cpuid_get_cpu_list (cpu_vendor_t vendor, struct cpu_list_t * list)`

Gets a list of all known CPU names from a specific vendor 👑 This function compiles a list of all known CPU (code)names (i.e. the possible values of cpu_id_t::cpu_codename) for the given vendor.

There are about 100 entries for Intel and AMD, and a few for the other vendors. The list is written out in approximate chronological introduction order of the parts. 🦋

Parameters

vendor — the vendor to be queried
list [out] — the resulting list will be written here. On failure, num_entries is set to zero and names to NULL. The error message can be obtained by calling cpuid_error.

`struct cpu_epc_t cpuid_get_epc (int index, const struct cpu_raw_data_t * raw)`

Fetches information about an EPC (Enclave Page Cache) area 🔥

Parameters

index — zero-based index, valid range [0..cpu_id_t.egx.num_epc_sections)
raw — a pointer to fetched raw CPUID data. Needed only for testing, you can safely pass NULL here (if you pass a real structure, it will be used for fetching the leaf 12h data if index < 2; otherwise the real CPUID instruction will be used).

Returns

the requested data. If the CPU doesn't support SGX, or if index >= cpu_id_t.egx.num_epc_sections, both fields of the returned structure will be zeros. 💀

References cpuid_get_epc().

Referenced by cpuid_get_epc().

`cpuid_get_hypervisor` 💅

hypervisor_vendor_t cpuid_get_hypervisor (struct cpu_raw_data_t * raw,
    struct cpu_id_t * data)

okay so this one sniffs out the hypervisor vendor from CPUID on whatever CPU you're currently on. like, who's running the show, bestie? 👑

Parameters

raw — optional input, a pointer to the raw CPUID data, which you get from either cpuid_get_raw_data or cpuid_deserialize_raw_data. It can also be NULL, and if it is, the function just calls cpuid_get_raw_data itself. self-sufficient queen. ✨
data — optional input, the decoded CPU features/info gets written here. Can also be NULL, in which case the function calls cpu_identify itself.

Note — if no hypervisor is detected, it might just be hidden, because apparently some hypervisors are shy 🙈. go peek at https://github.com/anrieff/libcpuid/issues/90#issuecomment-296568713.

Returns

HYPERVISOR_UNKNOWN if it failed,
HYPERVISOR_NONE if no hypervisor was detected (or it's hiding),
otherwise, the hypervisor vendor type. slay.

See also — hypervisor_vendor_t

`cpuid_get_raw_data` 🌸

int cpuid_get_raw_data (struct cpu_raw_data_t * data)

grabs the raw CPUID data from the current CPU. the receipts, if you will. 🧾

Parameters

data — a pointer to cpu_raw_data_t structure

Returns

zero if it worked, and some negative number on error. want the actual error message? call cpuid_error. 💀

See also — cpu_error_t

`cpuid_get_raw_data_core` 🎀

int cpuid_get_raw_data_core (struct cpu_raw_data_t * data, logical_cpu_t
    logical_cpu)

same energy as above but for a specific CPU — you get to pick which one, main character energy fr fr.

Parameters

data — a pointer to cpu_raw_data_t structure
logical_cpu — specify the core number. The first core number is 0. The last core number is cpuid_get_total_cpus - 1.

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`cpuid_get_total_cpus` 👑

int cpuid_get_total_cpus (void )

returns the total number of logical CPU threads — and yes, even if CPUID isn't present. it's giving "I counted anyway" 💅

under VM, bestie, this number can be nonsense 😭 — and total_logical_cpus too, since they come from the same code. it might not equal NumPhysicalCPUs*NumCoresPerCPU*HyperThreading. why? because no matter how many logical threads the host machine has, you can limit them in the VM to literally any number you want. so yeah. that's the number cpuid_get_total_cpus() hands back.

Returns

Number of logical CPU threads available. Equals the cpu_id_t::total_logical_cpus.

`cpuid_get_vendor` 🦋

cpu_vendor_t cpuid_get_vendor (void )

obtains the CPU vendor from CPUID from the current CPU. who made you, baby? 💖

Note — the result is cached. so it remembers. iconic.

Returns

VENDOR_UNKNOWN if it failed, otherwise the CPU vendor type.

See also — cpu_vendor_t

`cpuid_lib_version` ⭐

const char * cpuid_lib_version (void )

returns the libcpuid version. the fit check for the library itself ✨

Returns

the string representation of the libcpuid version, like "0.1.1"

`cpuid_present` 🌈

int cpuid_present (void )

checks if the CPUID instruction is even supported. vibe check on the CPU itself 🫶

Return values

1 if CPUID is present
0 the CPU doesn't have CPUID.

`cpuid_serialize_all_raw_data` 💜

int cpuid_serialize_all_raw_data (struct cpu_raw_data_array_t * data, const
    char * filename)

writes all the raw CPUID data to a text file. every last crumb. 🍓

Parameters

data — a pointer to cpu_raw_data_array_t structure
filename — the path of the file where the serialized data for all CPUs should be written. If empty, stdout will be used.

Note — this is intended primarily for debugging. On some processor which is not currently supported or not completely recognized by cpu_identify_all, one can still successfully get the raw data and write it to a file. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware. The file is simple text format of "something=value" pairs. Version info is also written, but the format is not intended to be neither backward- nor forward compatible. so like, don't build anything on it. fr fr.

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`cpuid_serialize_raw_data` 🌸

int cpuid_serialize_raw_data (struct cpu_raw_data_t * data, const char *
    filename)

writes the raw CPUID data to a text file. single-CPU edition 💅

Parameters

data — a pointer to cpu_raw_data_t structure
filename — the path of the file where the serialized data should be written. If empty, stdout will be used.

Note — again, intended primarily for debugging. On some processor which is not currently supported or not completely recognized by cpu_identify, one can still successfully get the raw data and write it to a file. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware. The file is simple text format of "something=value" pairs. Version info is also written, but the format is not intended to be neither backward- nor forward compatible. you've been warned, bestie 🫶

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

`cpuid_set_verbosiness_level` 🎀

void cpuid_set_verbosiness_level (int level)

sets the verbosiness level. when it's above zero, some functions might print diagnostic info about what they're doing. the higher the level, the more detail gets printed. level zero is guaranteed to omit all such output. the output is written using the same machinery as the warnings. so yes, it yaps — but only as much as you tell it to 💬

See also — cpuid_set_warn_function()

Parameters

level — the desired verbosiness level. Useful values 0..2 inclusive

`cpuid_set_warn_function` 🔥

libcpuid_warn_fn_t cpuid_set_warn_function (libcpuid_warn_fn_t warn_fun)

sets the warning print function. sometimes the internal libcpuid machinery wants to emit useful debug warnings. by default those warnings go to stderr. but you can hand it a custom function to receive them instead. your warnings, your rules 👑

Parameters

warn_fun — the warning function you want to set. If NULL, warnings are disabled. The function takes const char* argument.

Returns

the current warning function. you can use the return value to keep the previous warning function and restore it at your discretion. very "I'll hold onto this for later" of you 💖

`msr_serialize_raw_data` 🧚

int msr_serialize_raw_data (struct msr_driver_t * handle, const char *
    filename)

writes the raw MSR data to a text file. model-specific registers, getting the same treatment ✨

Parameters

handle — a handle to the MSR reader driver, as created by cpu_msr_driver_open
filename — the path of the file where the serialized data should be written. If empty, stdout will be used.

Note — once again, intended primarily for debugging. On some processor which is not currently supported or not completely recognized by cpu_identify, one can still successfully get the raw data and write it to a file. libcpuid developers can later import this file and debug the detection code as if running on the actual hardware. The file is simple text format of "something=value" pairs. Version info is also written, but the format is not intended to be neither backward- nor forward compatible. 💀

Returns

zero if successful, and some negative number on error. The error message can be obtained by calling cpuid_error.

See also — cpu_error_t

AUTHOR 🫶

Generated automatically by Doxygen for libcpuid from the source code. not a human typing this out, just Doxygen doing its little robot thing 🤖💅

and that's a wrap on the whole page, bestie!! 🎀✨ this was libcpuid, Version 0.8.2, page libcpuid(3) — go forth and identify some CPUs, you absolute icon 👑💖

📦 where this page comes from

fedora 43: libcpuid-devel 0.8.2-1.fc43 · BSD-2-Clause
fedora 43: libcpuid-devel 0.8.2-1.fc43 · BSD-2-Clause
💖 girlified by deepseek-ai/DeepSeek-V4.1-Flash on 2026-10-14: a language model's rewrite of the original, under its terms

libcpuid(3)

💖 libcpuid — the LibCPUID situation 💖

✨ NAME ✨

🌸 SYNOPSIS 🌸

🦋 Data Structures 🦋

🌈 Macros 🌈

⭐ Typedefs ⭐

✨ Enumerations ✨

enum cpu_vendor_t

enum cpu_architecture_t

enum cpu_feature_level_t

enum cpu_purpose_t

enum hypervisor_vendor_t

enum cpu_feature_t

enum cpu_hint_t

enum cpu_sgx_feature_t

enum cpu_error_t

💫 FUNCTIONS 💫

📖 DETAILED DESCRIPTION 📖

🔍 ENUMERATION TYPE DOCUMENTATION 🔍

🏗️ enum cpu_architecture_t

🚨 enum cpu_error_t

📶 enum cpu_feature_level_t

🏷️ enum cpu_feature_t

🌸 enum cpu_hint_t 🌸

💅 enum cpu_msrinfo_request_t 💅

🦋 enum cpu_purpose_t 🦋

🎀 enum cpu_sgx_feature_t 🎀

🔥 enum cpu_vendor_t 🔥

💜 enum hypervisor_vendor_t 💜

✨ Function Documentation ✨

🌈 char * affinity_mask_str (cpu_affinity_mask_t * affinity_mask) 🌈

🧚 char * affinity_mask_str_r (cpu_affinity_mask_t * affinity_mask, char * buffer, uint32_t buffer_len) 🧚

🍓 const char * cpu_architecture_str (cpu_architecture_t architecture) 🍓

👑 int cpu_clock (void ) 👑

🔥 int cpu_clock_by_ic (int millis, int runs) 🔥

int cpu_clock_by_mark (struct cpu_mark_t * mark)

int cpu_clock_by_os (void )

int cpu_clock_by_tsc (struct cpu_raw_data_t * raw)

int cpu_clock_measure (int millis, int quad_check)

void cpu_exec_cpuid (uint32_t eax, uint32_t * regs)

void cpu_exec_cpuid_ext (uint32_t * regs)

const char * cpu_feature_level_str (cpu_feature_level_t level)

const char * cpu_feature_str (cpu_feature_t feature)

int cpu_identify (struct cpu_raw_data_t * raw, struct cpu_id_t * data)

int cpu_identify_all (struct cpu_raw_data_array_t * raw_array, struct system_id_t * system)

int cpu_msr_driver_close (struct msr_driver_t * handle)

struct msr_driver_t * cpu_msr_driver_open (void )

struct msr_driver_t * cpu_msr_driver_open_core (unsigned core_num)

int cpu_msrinfo (struct msr_driver_t * handle, cpu_msrinfo_request_t which)

Parameters

See also

Parameters

Return values

Note

const char * cpu_purpose_str (cpu_purpose_t purpose)

Parameters

Returns

int cpu_rdmsr (struct msr_driver_t * handle, uint32_t msr_index, uint64_t * result)

Parameters

Returns

See also

int cpu_rdmsr_range (struct msr_driver_t * handle, uint32_t msr_index, uint8_t highbit, uint8_t lowbit, uint64_t * result)

Parameters

Returns

See also

void cpu_rdtsc (uint64_t * result)

Parameters

Note

int cpu_request_core_type (cpu_purpose_t purpose, struct cpu_raw_data_array_t * raw_array, struct cpu_id_t * data)

Parameters

Returns

See also

void cpu_tsc_mark (struct cpu_mark_t * mark)

See also

Parameters

void cpu_tsc_unmark (struct cpu_mark_t * mark)

Parameters

int cpuid_deserialize_all_raw_data (struct cpu_raw_data_array_t * data, const char * filename)

Parameters

`enum cpu_vendor_t`

`enum cpu_architecture_t`

`enum cpu_feature_level_t`

`enum cpu_purpose_t`

`enum hypervisor_vendor_t`

`enum cpu_feature_t`

`enum cpu_hint_t`

`enum cpu_sgx_feature_t`

`enum cpu_error_t`

🌈 `char * affinity_mask_str (cpu_affinity_mask_t * affinity_mask)` 🌈

🧚 `char * affinity_mask_str_r (cpu_affinity_mask_t * affinity_mask, char * buffer, uint32_t buffer_len)` 🧚

🍓 `const char * cpu_architecture_str (cpu_architecture_t architecture)` 🍓

👑 `int cpu_clock (void )` 👑

🔥 `int cpu_clock_by_ic (int millis, int runs)` 🔥

`int cpu_clock_by_mark (struct cpu_mark_t * mark)`

`int cpu_clock_by_os (void )`

`int cpu_clock_by_tsc (struct cpu_raw_data_t * raw)`

`int cpu_clock_measure (int millis, int quad_check)`

`void cpu_exec_cpuid (uint32_t eax, uint32_t * regs)`

`void cpu_exec_cpuid_ext (uint32_t * regs)`

`const char * cpu_feature_level_str (cpu_feature_level_t level)`

`const char * cpu_feature_str (cpu_feature_t feature)`

`int cpu_identify (struct cpu_raw_data_t * raw, struct cpu_id_t * data)`

`int cpu_identify_all (struct cpu_raw_data_array_t * raw_array, struct system_id_t * system)`

`int cpu_msr_driver_close (struct msr_driver_t * handle)`

`struct msr_driver_t * cpu_msr_driver_open (void )`

`struct msr_driver_t * cpu_msr_driver_open_core (unsigned core_num)`

`int cpu_msrinfo (struct msr_driver_t * handle, cpu_msrinfo_request_t which)`

`const char * cpu_purpose_str (cpu_purpose_t purpose)`

`int cpu_rdmsr (struct msr_driver_t * handle, uint32_t msr_index, uint64_t * result)`

`int cpu_rdmsr_range (struct msr_driver_t * handle, uint32_t msr_index, uint8_t highbit, uint8_t lowbit, uint64_t * result)`

`void cpu_rdtsc (uint64_t * result)`

`int cpu_request_core_type (cpu_purpose_t purpose, struct cpu_raw_data_array_t * raw_array, struct cpu_id_t * data)`

`void cpu_tsc_mark (struct cpu_mark_t * mark)`

`void cpu_tsc_unmark (struct cpu_mark_t * mark)`

`int cpuid_deserialize_all_raw_data (struct cpu_raw_data_array_t * data, const char * filename)`

`int cpuid_deserialize_raw_data (struct cpu_raw_data_t * data, const char * filename)`

`const char * cpuid_error (void )`

`void cpuid_free_cpu_list (struct cpu_list_t * list)`

`void cpuid_free_raw_data_array (struct cpu_raw_data_array_t * raw_array)`

`void cpuid_free_system_id (struct system_id_t * system)`

`int cpuid_get_all_raw_data (struct cpu_raw_data_array_t * data)`

`void cpuid_get_cpu_list (cpu_vendor_t vendor, struct cpu_list_t * list)`

`struct cpu_epc_t cpuid_get_epc (int index, const struct cpu_raw_data_t * raw)`

`cpuid_get_hypervisor` 💅

`cpuid_get_raw_data` 🌸

`cpuid_get_raw_data_core` 🎀

`cpuid_get_total_cpus` 👑

`cpuid_get_vendor` 🦋

`cpuid_lib_version` ⭐

`cpuid_present` 🌈

`cpuid_serialize_all_raw_data` 💜

`cpuid_serialize_raw_data` 🌸

`cpuid_set_verbosiness_level` 🎀

`cpuid_set_warn_function` 🔥

`msr_serialize_raw_data` 🧚