constants(3)

📦
version 1.75 · 4 versions
, in debian trixie, ubuntu noble, ubuntu questing

💖 constants 💖

okay bestie, welcome to constants(3) — straight out of the Library Functions Manual fr fr 🎀

✨ NAME ✨

constants — the constants you pass to library functions, and the constants you get back from them 🫶

no cap, that's the whole vibe of this page: it's your lil directory of all the named values that go into library calls and come out of them. iykyk 💅

more parts are coming, so don't go anywhere — we're just getting started ✨🦋

🌸 SYNOPSIS 🌸

okay so. this page does not ease you in. it just tips the entire dictionary onto your desk and goes "there bestie, memorize." 💀

everything below is a macro from the library's header — literally every name it answers to, paired with the exact number it's hiding. do not retype these by hand, just #include the header and let it cook. 🍓

✨ Macros ✨

🎀 the baby ones

#define HIGH   0x1
#define LOW   0x0
#define MIN(a,  b)   (a < b ? a : b)

HIGH and LOW are the two moods. MIN(a, b) is the tiniest "whichever's smaller, babe" macro — and yes, the double space inside the argument list is literally in the source, leave it alone, it's part of the aesthetic. 💅

then the clock + address lore drops:

#define BCM2835_CORE_CLK_HZ   250000000
#define BMC2835_RPI2_DT_FILENAME   '/proc/device-tree/soc/ranges'
#define BCM2835_PERI_BASE   0x20000000
#define BCM2835_PERI_SIZE   0x01000000
#define BCM2835_RPI2_PERI_BASE   0x3F000000
#define BCM2835_RPI4_PERI_BASE   0xFE000000
#define BCM2835_RPI4_PERI_SIZE   0x01800000
not me clocking that BMC2835_RPI2_DT_FILENAME is genuinely spelled BMC and not BCM. that is not my typo, that is the actual name, no cap. spell it exactly like that or the compiler will simply not know her. 😭

🗺️ where everything lives (the base addresses)

this is the map, bestie. every peripheral gets a little plot of memory and these are the street numbers. 🏡

#define BCM2835_ST_BASE   0x3000
#define BCM2835_GPIO_PADS   0x100000
#define BCM2835_CLOCK_BASE   0x101000
#define BCM2835_GPIO_BASE   0x200000
#define BCM2835_SPI0_BASE   0x204000
#define BCM2835_BSC0_BASE   0x205000
#define BCM2835_GPIO_PWM   0x20C000
#define BCM2835_AUX_BASE   0x215000
#define BCM2835_SPI1_BASE   0x215080
#define BCM2835_SPI2_BASE   0x2150C0
#define BCM2835_BSC1_BASE   0x804000
#define BCM2835_SMI_BASE   0x600000
#define BCM2835_PAGE_SIZE   (4*1024)
#define BCM2835_BLOCK_SIZE   (4*1024)

PAGE_SIZE and BLOCK_SIZE are both (4*1024), so yes, they're twins. matching. slay. ✨

💖 the GPIO register wall

this is the big one, the main character. forty-ish defines of pure GPIO energy. every single one, exactly as written, zero skips: 🫶

#define BCM2835_GPFSEL0   0x0000
#define BCM2835_GPFSEL1   0x0004
#define BCM2835_GPFSEL2   0x0008
#define BCM2835_GPFSEL3   0x000c
#define BCM2835_GPFSEL4   0x0010
#define BCM2835_GPFSEL5   0x0014
#define BCM2835_GPSET0   0x001c
#define BCM2835_GPSET1   0x0020
#define BCM2835_GPCLR0   0x0028
#define BCM2835_GPCLR1   0x002c
#define BCM2835_GPLEV0   0x0034
#define BCM2835_GPLEV1   0x0038
#define BCM2835_GPEDS0   0x0040
#define BCM2835_GPEDS1   0x0044
#define BCM2835_GPREN0   0x004c
#define BCM2835_GPREN1   0x0050
#define BCM2835_GPFEN0   0x0058
#define BCM2835_GPFEN1   0x005c
#define BCM2835_GPHEN0   0x0064
#define BCM2835_GPHEN1   0x0068
#define BCM2835_GPLEN0   0x0070
#define BCM2835_GPLEN1   0x0074
#define BCM2835_GPAREN0   0x007c
#define BCM2835_GPAREN1   0x0080
#define BCM2835_GPAFEN0   0x0088
#define BCM2835_GPAFEN1   0x008c
#define BCM2835_GPPUD   0x0094
#define BCM2835_GPPUDCLK0   0x0098
#define BCM2835_GPPUDCLK1   0x009c
#define BCM2835_GPPUPPDN0   0x00e4 /* Pin pull-up/down for pins 15:0  */
#define BCM2835_GPPUPPDN1   0x00e8 /* Pin pull-up/down for pins 31:16 */
#define BCM2835_GPPUPPDN2   0x00ec /* Pin pull-up/down for pins 47:32 */
#define BCM2835_GPPUPPDN3   0x00f0 /* Pin pull-up/down for pins 57:48 */
#define BCM2835_GPIO_PUD_ERROR   0x08

the last four come with their own little pinned-on notes about which pins they cover — 15:0, 31:16, 47:32, 57:48 — keep them attached, they're load-bearing. 🎀

🌈 the pads (yes, pads)

#define BCM2835_PADS_GPIO_0_27   0x002c
#define BCM2835_PADS_GPIO_28_45   0x0030
#define BCM2835_PADS_GPIO_46_53   0x0034
#define BCM2835_PAD_PASSWRD   (0x5A << 24)
#define BCM2835_PAD_SLEW_RATE_UNLIMITED   0x10
#define BCM2835_PAD_HYSTERESIS_ENABLED   0x08
#define BCM2835_PAD_DRIVE_2mA   0x00
#define BCM2835_PAD_DRIVE_4mA   0x01
#define BCM2835_PAD_DRIVE_6mA   0x02
#define BCM2835_PAD_DRIVE_8mA   0x03
#define BCM2835_PAD_DRIVE_10mA   0x04
#define BCM2835_PAD_DRIVE_12mA   0x05
#define BCM2835_PAD_DRIVE_14mA   0x06
#define BCM2835_PAD_DRIVE_16mA   0x07

a whole lil ladder of drive strengths from 2mA all the way up to 16mA, each one counting up by exactly one. the way that's so satisfying. 👑

🦋 AUX, the side-quest peripheral

#define BCM2835_AUX_IRQ   0x0000
#define BCM2835_AUX_ENABLE   0x0004
#define BCM2835_AUX_ENABLE_UART1   0x01
#define BCM2835_AUX_ENABLE_SPI0   0x02
#define BCM2835_AUX_ENABLE_SPI1   0x04
#define BCM2835_AUX_SPI_CNTL0   0x0000
#define BCM2835_AUX_SPI_CNTL1   0x0004
#define BCM2835_AUX_SPI_STAT   0x0008
#define BCM2835_AUX_SPI_PEEK   0x000C
#define BCM2835_AUX_SPI_IO   0x0020
#define BCM2835_AUX_SPI_TXHOLD   0x0030
#define BCM2835_AUX_SPI_CLOCK_MIN   30500
#define BCM2835_AUX_SPI_CLOCK_MAX   125000000

then the CNTL0 bit zoo — speeds, chip selects, phase, polarity, all of it:

#define BCM2835_AUX_SPI_CNTL0_SPEED   0xFFF00000
#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX   0xFFF
#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT   20
#define BCM2835_AUX_SPI_CNTL0_CS0_N   0x000C0000
#define BCM2835_AUX_SPI_CNTL0_CS1_N   0x000A0000
#define BCM2835_AUX_SPI_CNTL0_CS2_N   0x00060000
#define BCM2835_AUX_SPI_CNTL0_POSTINPUT   0x00010000
#define BCM2835_AUX_SPI_CNTL0_VAR_CS   0x00008000
#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH   0x00004000
#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD   0x00003000
#define BCM2835_AUX_SPI_CNTL0_ENABLE   0x00000800
#define BCM2835_AUX_SPI_CNTL0_CPHA_IN   0x00000400
#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO   0x00000200
#define BCM2835_AUX_SPI_CNTL0_CPHA_OUT   0x00000100
#define BCM2835_AUX_SPI_CNTL0_CPOL   0x00000080
#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT   0x00000040
#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN   0x0000003F

and CNTL1:

#define BCM2835_AUX_SPI_CNTL1_CSHIGH   0x00000700
#define BCM2835_AUX_SPI_CNTL1_IDLE   0x00000080
#define BCM2835_AUX_SPI_CNTL1_TXEMPTY   0x00000040
#define BCM2835_AUX_SPI_CNTL1_MSBF_IN   0x00000002
#define BCM2835_AUX_SPI_CNTL1_KEEP_IN   0x00000001

and the status crew, who will absolutely be telling you how it's going:

#define BCM2835_AUX_SPI_STAT_TX_LVL   0xF0000000
#define BCM2835_AUX_SPI_STAT_RX_LVL   0x00F00000
#define BCM2835_AUX_SPI_STAT_TX_FULL   0x00000400
#define BCM2835_AUX_SPI_STAT_TX_EMPTY   0x00000200
#define BCM2835_AUX_SPI_STAT_RX_FULL   0x00000100
#define BCM2835_AUX_SPI_STAT_RX_EMPTY   0x00000080
#define BCM2835_AUX_SPI_STAT_BUSY   0x00000040
#define BCM2835_AUX_SPI_STAT_BITCOUNT   0x0000003F

🔥 SPI0, the main SPI

#define BCM2835_SPI0_CS   0x0000
#define BCM2835_SPI0_FIFO   0x0004
#define BCM2835_SPI0_CLK   0x0008
#define BCM2835_SPI0_DLEN   0x000c
#define BCM2835_SPI0_LTOH   0x0010
#define BCM2835_SPI0_DC   0x0014
#define BCM2835_SPI0_CS_LEN_LONG   0x02000000
#define BCM2835_SPI0_CS_DMA_LEN   0x01000000
#define BCM2835_SPI0_CS_CSPOL2   0x00800000
#define BCM2835_SPI0_CS_CSPOL1   0x00400000
#define BCM2835_SPI0_CS_CSPOL0   0x00200000
#define BCM2835_SPI0_CS_RXF   0x00100000
#define BCM2835_SPI0_CS_RXR   0x00080000
#define BCM2835_SPI0_CS_TXD   0x00040000
#define BCM2835_SPI0_CS_RXD   0x00020000
#define BCM2835_SPI0_CS_DONE   0x00010000
#define BCM2835_SPI0_CS_TE_EN   0x00008000
#define BCM2835_SPI0_CS_LMONO   0x00004000
#define BCM2835_SPI0_CS_LEN   0x00002000
#define BCM2835_SPI0_CS_REN   0x00001000
#define BCM2835_SPI0_CS_ADCS   0x00000800
#define BCM2835_SPI0_CS_INTR   0x00000400
#define BCM2835_SPI0_CS_INTD   0x00000200
#define BCM2835_SPI0_CS_DMAEN   0x00000100
#define BCM2835_SPI0_CS_TA   0x00000080
#define BCM2835_SPI0_CS_CSPOL   0x00000040
#define BCM2835_SPI0_CS_CLEAR   0x00000030
#define BCM2835_SPI0_CS_CLEAR_RX   0x00000020
#define BCM2835_SPI0_CS_CLEAR_TX   0x00000010
#define BCM2835_SPI0_CS_CPOL   0x00000008
#define BCM2835_SPI0_CS_CPHA   0x00000004
#define BCM2835_SPI0_CS_CS   0x00000003

the way CS_CLEAR is 0x00000030 and then CLEAR_RX is 0x00000020 and CLEAR_TX is 0x00000010 — it's giving "one mask, two bits" and it's correct. 🌈

🧚 BSC (the I²C girlies)

#define BCM2835_BSC_C   0x0000
#define BCM2835_BSC_S   0x0004
#define BCM2835_BSC_DLEN   0x0008
#define BCM2835_BSC_A   0x000c
#define BCM2835_BSC_FIFO   0x0010
#define BCM2835_BSC_DIV   0x0014
#define BCM2835_BSC_DEL   0x0018
#define BCM2835_BSC_CLKT   0x001c
#define BCM2835_BSC_C_I2CEN   0x00008000
#define BCM2835_BSC_C_INTR   0x00000400
#define BCM2835_BSC_C_INTT   0x00000200
#define BCM2835_BSC_C_INTD   0x00000100
#define BCM2835_BSC_C_ST   0x00000080
#define BCM2835_BSC_C_CLEAR_1   0x00000020
#define BCM2835_BSC_C_CLEAR_2   0x00000010
#define BCM2835_BSC_C_READ   0x00000001
#define BCM2835_BSC_S_CLKT   0x00000200
#define BCM2835_BSC_S_ERR   0x00000100
#define BCM2835_BSC_S_RXF   0x00000080
#define BCM2835_BSC_S_TXE   0x00000040
#define BCM2835_BSC_S_RXD   0x00000020
#define BCM2835_BSC_S_TXD   0x00000010
#define BCM2835_BSC_S_RXR   0x00000008
#define BCM2835_BSC_S_TXW   0x00000004
#define BCM2835_BSC_S_DONE   0x00000002
#define BCM2835_BSC_S_TA   0x00000001
#define BCM2835_BSC_FIFO_SIZE   16
#define BCM2835_AUX_SPI_FIFO_SIZE   4

two FIFO sizes at the bottom, 16 for BSC and 4 for the AUX SPI, because they are not the same girl and should not be treated as the same girl. 🙈

💜 SMI, the deep lore

these ones come with their own inline doc comments, so i'm passing them straight through — every /*! < … > */ preserved, every weird spacing intact, because that's how she wrote them:

#define BCM2835_SMI_CS   0          /*! < Control and status register > */
#define BCM2835_SMI_LENGTH   1          /*! < Transfer length register > */
#define BCM2835_SMI_ADRS   2          /*! < Transfer address register > */
#define BCM2835_SMI_DATA   3          /*! < Transfer data register > */
#define BCM2835_SMI_READ0   4          /*! < Read  settings 0 register > */
#define BCM2835_SMI_WRITE0   5          /*! < Write settings 0 register > */
#define BCM2835_SMI_READ1   6          /*! < Read  settings 1 register > */
#define BCM2835_SMI_WRITE1   7          /*! < Write settings 1 register > */
#define BCM2835_SMI_READ2   8          /*! < Read  settings 2 register > */
#define BCM2835_SMI_WRITE2   9          /*! < Write settings 2 register > */
#define BCM2835_SMI_READ3   10          /*! < Read  settings 3 register > */
#define BCM2835_SMI_WRITE3   11          /*! < Write settings 3 register > */
#define BCM2835_SMI_DMAC   12          /*! < DMA control register > */
#define BCM2835_SMI_DIRCS   13          /*! < Direct control register > */
#define BCM2835_SMI_DIRADDR   14          /*! < Direct access address register > */
#define BCM2835_SMI_DIRDATA   15          /*! < Direct access data register > */

note how READ0 through READ3 each have two spaces before "settings" in the comment, while the WRITE ones have one. that's not me being chaotic, that's the source being chaotic. matching energy. 💅

now the read/write bit fields:

#define BCM2835_SMI_RW_WIDTH_MSK   0xC0000000 /*! < Data width mask > */
#define BCM2835_SMI_RW_WID8   0x00000000 /*! < Data width 8 bits > */
#define BCM2835_SMI_RW_WID16   0x40000000 /*! < Data width 16 bits > */
#define BCM2835_SMI_RW_WID18   0x80000000 /*! < Data width 18 bits > */
#define BCM2835_SMI_RW_WID9   0xC0000000 /*! < Data width 9 bits > */
#define BCM2835_SMI_RW_SETUP_MSK   0x3F000000 /*! < Setup cycles (6 bits) > */
#define BCM2835_SMI_RW_SETUP_LS   24         /*! < Shift for setup cycles > */
#define BCM2835_SMI_RW_MODE68   0x00800000 /*! < Run cycle motorola mode > */
#define BCM2835_SMI_RW_MODE80   0x00000000 /*! < Run cycle intel mode > */
#define BCM2835_SMI_READ_FSETUP   0x00400000 /*! < Read : Setup only for first cycle > */
#define BCM2835_SMI_WRITE_SWAP   0x00400000 /*! < Write : swap pixel data > */
#define BCM2835_SMI_RW_HOLD_MSK   0x003F0000 /*! < Hold cycles (6 bits) > */
#define BCM2835_SMI_RW_HOLD_LS   16         /*! < Shift for hold cycles > */
#define BCM2835_SMI_RW_PACEALL   0x00008000 /*! < Apply pacing always > */
#define BCM2835_SMI_RW_PACE_MSK   0x00007F00 /*! < Pace cycles (7 bits) > */
#define BCM2835_SMI_RW_PACE_LS   8          /*! < Shift for pace cycles > */
#define BCM2835_SMI_RW_DREQ   0x00000080 /*! < Use DMA req on read/write > */
#define BCM2835_SMI_RW_STROBE_MSK   0x0000007F /*! < Strobe cycles (7 bits) > */
#define BCM2835_SMI_RW_STROBE_LS   0          /*! < Shift for strobe cycles > */

READ_FSETUP and WRITE_SWAP are both 0x00400000 — same number, different meaning depending on which way the data's going. it's giving "shared address, twin destinies". 🦋

and finally the direct-control flags:

#define BCM2835_SMI_DIRCS_ENABLE   0x00000001  /*! < Set to enable SMI. 0 = Read from ext. devices > */
#define BCM2835_SMI_DIRCS_START   0x00000002  /*! < Initiate SMI transfer > */
#define BCM2835_SMI_DIRCS_DONE   0x00000004  /*! < Set if transfer has finished / Write to clear flag > */
heads up bestie: DIRCS_DONE is a read-to-check, write-to-clear flag. so if you're just sitting there reading it and wondering why it never goes away — yeah, you have to write to it. that's not a bug, that's the deal. 😭

those three all use two spaces before their comment, unlike basically everything else on this page. i don't make the rules. i just report them. ✨

  • BCM2835_SMI_DIRCS_WRITE = 0x00000008 — 1 = write out to ext. devices 📤
  • BCM2835_SMI_DIRADRS_DEV_MSK = 0x00000300 — the mask for the timing configuration slot 🎚️
  • BCM2835_SMI_DIRADRS_DEV_LS = 8 — how far you shift to get at that configuration slot
  • BCM2835_SMI_DIRADRS_DEV0 = 0x00000000 — use timing config slot 0 🕐
  • BCM2835_SMI_DIRADRS_DEV1 = 0x00000100 — use timing config slot 1
  • BCM2835_SMI_DIRADRS_DEV2 = 0x00000200 — use timing config slot 2
  • BCM2835_SMI_DIRADRS_DEV3 = 0x00000300 — use timing config slot 3
  • BCM2835_SMI_DIRADRS_MSK = 0x0000003F — adress bits SA5..SA0 (yes bestie, the original really spells it "Adress", we do not correct the ancestors 😌)
  • BCM2835_SMI_DIRADRS_LS = 0 — shift for the address bits
  • SMICLK_CNTL = (44) — /* = 0xB0 */ 🎛️
  • SMICLK_DIV = (45) — /* = 0xB4 */
  • BCM2835_ST_CS = 0x0000
  • BCM2835_ST_CLO = 0x0004
  • BCM2835_ST_CHI = 0x0008

✨ Enumerations ✨

Okay this is the part where the library hands you a menu of vibes and you just pick one. Each one is a type you pass to a specific function, so clock the typedef names, they're the receipts 🧾

  • enum bcm2835RegisterBase — register bases for bcm2835_regbase(). Typedef'd as bcm2835RegisterBase.
enum bcm2835RegisterBase {
    BCM2835_REGBASE_ST   = 1,
    BCM2835_REGBASE_GPIO = 2,
    BCM2835_REGBASE_PWM  = 3,
    BCM2835_REGBASE_CLK  = 4,
    BCM2835_REGBASE_PADS = 5,
    BCM2835_REGBASE_SPI0 = 6,
    BCM2835_REGBASE_BSC0 = 7,
    BCM2835_REGBASE_BSC1 = 8,
    BCM2835_REGBASE_AUX  = 9,
    BCM2835_REGBASE_SPI1 = 10,
    BCM2835_REGBASE_SMI  = 11
};
  • enum bcm2835FunctionSelect — port function select modes for bcm2835_gpio_fsel(). Typedef'd as bcm2835PortFunction.
enum bcm2835FunctionSelect {
    BCM2835_GPIO_FSEL_INPT = 0x00,
    BCM2835_GPIO_FSEL_OUTP = 0x01,
    BCM2835_GPIO_FSEL_ALT0 = 0x04,
    BCM2835_GPIO_FSEL_ALT1 = 0x05,
    BCM2835_GPIO_FSEL_ALT2 = 0x06,
    BCM2835_GPIO_FSEL_ALT3 = 0x07,
    BCM2835_GPIO_FSEL_ALT4 = 0x03,
    BCM2835_GPIO_FSEL_ALT5 = 0x02,
    BCM2835_GPIO_FSEL_MASK = 0x07
};
Not me noticing ALT4 and ALT5 are 0x03 and 0x02 while ALT3 is 0x07 💀 the numbering is NOT in order bestie, do not assume, just use the names.
  • enum bcm2835PUDControl — pullup/pulldown defines for bcm2835_gpio_pud(). Typedef'd as bcm2835PUDControl.
enum bcm2835PUDControl {
    BCM2835_GPIO_PUD_OFF  = 0x00,
    BCM2835_GPIO_PUD_DOWN = 0x01,
    BCM2835_GPIO_PUD_UP   = 0x02
};
  • enum bcm2835PadGroup — pad group specification for bcm2835_gpio_pad(). Typedef'd as bcm2835PadGroup.
enum bcm2835PadGroup {
    BCM2835_PAD_GROUP_GPIO_0_27  = 0,
    BCM2835_PAD_GROUP_GPIO_28_45 = 1,
    BCM2835_PAD_GROUP_GPIO_46_53 = 2
};
  • enum RPiGPIOPin — GPIO pin numbers. This one is LONG, it's giving phone book energy, but every single one is here fr fr 📞
enum RPiGPIOPin {
    RPI_GPIO_P1_03  = 0,
    RPI_GPIO_P1_05  = 1,
    RPI_GPIO_P1_07  = 4,
    RPI_GPIO_P1_08  = 14,
    RPI_GPIO_P1_10  = 15,
    RPI_GPIO_P1_11  = 17,
    RPI_GPIO_P1_12  = 18,
    RPI_GPIO_P1_13  = 21,
    RPI_GPIO_P1_15  = 22,
    RPI_GPIO_P1_16  = 23,
    RPI_GPIO_P1_18  = 24,
    RPI_GPIO_P1_19  = 10,
    RPI_GPIO_P1_21  = 9,
    RPI_GPIO_P1_22  = 25,
    RPI_GPIO_P1_23  = 11,
    RPI_GPIO_P1_24  = 8,
    RPI_GPIO_P1_26  = 7,
    RPI_V2_GPIO_P1_03 = 2,
    RPI_V2_GPIO_P1_05 = 3,
    RPI_V2_GPIO_P1_07 = 4,
    RPI_V2_GPIO_P1_08 = 14,
    RPI_V2_GPIO_P1_10 = 15,
    RPI_V2_GPIO_P1_11 = 17,
    RPI_V2_GPIO_P1_12 = 18,
    RPI_V2_GPIO_P1_13 = 27,
    RPI_V2_GPIO_P1_15 = 22,
    RPI_V2_GPIO_P1_16 = 23,
    RPI_V2_GPIO_P1_18 = 24,
    RPI_V2_GPIO_P1_19 = 10,
    RPI_V2_GPIO_P1_21 = 9,
    RPI_V2_GPIO_P1_22 = 25,
    RPI_V2_GPIO_P1_23 = 11,
    RPI_V2_GPIO_P1_24 = 8,
    RPI_V2_GPIO_P1_26 = 7,
    RPI_V2_GPIO_P1_29 = 5,
    RPI_V2_GPIO_P1_31 = 6,
    RPI_V2_GPIO_P1_32 = 12,
    RPI_V2_GPIO_P1_33 = 13,
    RPI_V2_GPIO_P1_35 = 19,
    RPI_V2_GPIO_P1_36 = 16,
    RPI_V2_GPIO_P1_37 = 26,
    RPI_V2_GPIO_P1_38 = 20,
    RPI_V2_GPIO_P1_40 = 21,
    RPI_V2_GPIO_P5_03 = 28,
    RPI_V2_GPIO_P5_04 = 29,
    RPI_V2_GPIO_P5_05 = 30,
    RPI_V2_GPIO_P5_06 = 31,
    RPI_BPLUS_GPIO_J8_03 = 2,
    RPI_BPLUS_GPIO_J8_05 = 3,
    RPI_BPLUS_GPIO_J8_07 = 4,
    RPI_BPLUS_GPIO_J8_08 = 14,
    RPI_BPLUS_GPIO_J8_10 = 15,
    RPI_BPLUS_GPIO_J8_11 = 17,
    RPI_BPLUS_GPIO_J8_12 = 18,
    RPI_BPLUS_GPIO_J8_13 = 27,
    RPI_BPLUS_GPIO_J8_15 = 22,
    RPI_BPLUS_GPIO_J8_16 = 23,
    RPI_BPLUS_GPIO_J8_18 = 24,
    RPI_BPLUS_GPIO_J8_19 = 10,
    RPI_BPLUS_GPIO_J8_21 = 9,
    RPI_BPLUS_GPIO_J8_22 = 25,
    RPI_BPLUS_GPIO_J8_23 = 11,
    RPI_BPLUS_GPIO_J8_24 = 8,
    RPI_BPLUS_GPIO_J8_26 = 7,
    RPI_BPLUS_GPIO_J8_29 = 5,
    RPI_BPLUS_GPIO_J8_31 = 6,
    RPI_BPLUS_GPIO_J8_32 = 12,
    RPI_BPLUS_GPIO_J8_33 = 13,
    RPI_BPLUS_GPIO_J8_35 = 19,
    RPI_BPLUS_GPIO_J8_36 = 16,
    RPI_BPLUS_GPIO_J8_37 = 26,
    RPI_BPLUS_GPIO_J8_38 = 20,
    RPI_BPLUS_GPIO_J8_40 = 21
};
  • enum bcm2835SPIBitOrder — SPI bit order: specifies the SPI data bit ordering for bcm2835_spi_setBitOrder(). Typedef'd as bcm2835SPIBitOrder.
enum bcm2835SPIBitOrder {
    BCM2835_SPI_BIT_ORDER_LSBFIRST = 0,
    BCM2835_SPI_BIT_ORDER_MSBFIRST = 1
};
  • enum bcm2835SPIMode — SPI data mode: specifies the SPI data mode to hand over to bcm2835_spi_setDataMode().
enum bcm2835SPIMode {
    BCM2835_SPI_MODE0 = 0,
    BCM2835_SPI_MODE1 = 1,
    BCM2835_SPI_MODE2 = 2,
    BCM2835_SPI_MODE3 = 3
};
  • enum bcm2835SPIChipSelect — specify the SPI chip select pin(s). Typedef'd as bcm2835SPIChipSelect.
enum bcm2835SPIChipSelect {
    BCM2835_SPI_CS0    = 0,
    BCM2835_SPI_CS1    = 1,
    BCM2835_SPI_CS2    = 2,
    BCM2835_SPI_CS_NONE = 3
};
  • enum bcm2835SPIClockDivider — the divider used to generate the SPI clock from the system clock. Typedef'd as bcm2835SPIClockDivider. The figures below give the divider, clock period and clock frequency. Clock divided is based on nominal core clock rate of 250MHz on RPi1 and RPi2, and 400MHz on RPi3. It is reported that (contrary to the documentation) any even divider may be used. The frequencies shown for each divider have been confirmed by measurement on RPi1 and RPi2. The system clock frequency on RPi3 is different, so the frequency you get from a given divider will be different. See comments in 'SPI Pins' for information about reliable SPI speeds. Note: it is possible to change the core clock rate of the RPi 3 back to 250MHz, by putting
enum bcm2835SPIClockDivider {
    BCM2835_SPI_CLOCK_DIVIDER_65536 = 0,
    BCM2835_SPI_CLOCK_DIVIDER_32768 = 32768,
    BCM2835_SPI_CLOCK_DIVIDER_16384 = 16384,
    BCM2835_SPI_CLOCK_DIVIDER_8192  = 8192,
    BCM2835_SPI_CLOCK_DIVIDER_4096  = 4096,
    BCM2835_SPI_CLOCK_DIVIDER_2048  = 2048,
    BCM2835_SPI_CLOCK_DIVIDER_1024  = 1024,
    BCM2835_SPI_CLOCK_DIVIDER_512   = 512,
    BCM2835_SPI_CLOCK_DIVIDER_256   = 256,
    BCM2835_SPI_CLOCK_DIVIDER_128   = 128,
    BCM2835_SPI_CLOCK_DIVIDER_64    = 64,
    BCM2835_SPI_CLOCK_DIVIDER_32    = 32,
    BCM2835_SPI_CLOCK_DIVIDER_16    = 16,
    BCM2835_SPI_CLOCK_DIVIDER_8     = 8,
    BCM2835_SPI_CLOCK_DIVIDER_4     = 4,
    BCM2835_SPI_CLOCK_DIVIDER_2     = 2,
    BCM2835_SPI_CLOCK_DIVIDER_1     = 1
};
Bestie the 65536 one is 0, not 65536 💀 that's not a typo on my end, that's literally what it says. Read the numbers, don't vibe-guess them.
  • enum bcm2835I2CClockDivider — the divider used to generate the I2C clock from the system clock. Clock divided is based on nominal base clock rate of 250MHz. Typedef'd as bcm2835I2CClockDivider.
enum bcm2835I2CClockDivider {
    BCM2835_I2C_CLOCK_DIVIDER_2500 = 2500,
    BCM2835_I2C_CLOCK_DIVIDER_626  = 626,
    BCM2835_I2C_CLOCK_DIVIDER_150  = 150,
    BCM2835_I2C_CLOCK_DIVIDER_148  = 148
};
  • enum bcm2835I2CReasonCodes — the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions. Typedef'd as bcm2835I2CReasonCodes.
enum bcm2835I2CReasonCodes {
    BCM2835_I2C_REASON_OK            = 0x00,
    BCM2835_I2C_REASON_ERROR_NACK    = 0x01,
    BCM2835_I2C_REASON_ERROR_CLKT    = 0x02,
    BCM2835_I2C_REASON_ERROR_DATA    = 0x04,
    BCM2835_I2C_REASON_ERROR_TIMEOUT = 0x08
};

🦋 Variables 🦋

These are the library's global girlies — pointers and sizes just hanging out in the open, ready to be read. Note who's volatile and who isn't, that's on purpose 👀

  • off_t bcm2835_peripherals_base
  • size_t bcm2835_peripherals_size
  • uint32_t * bcm2835_peripherals
  • volatile uint32_t * bcm2835_st
  • volatile uint32_t * bcm2835_gpio
  • volatile uint32_t * bcm2835_pwm
  • volatile uint32_t * bcm2835_clk
  • volatile uint32_t * bcm2835_pads
  • volatile uint32_t * bcm2835_spi0
  • volatile uint32_t * bcm2835_bsc0
  • volatile uint32_t * bcm2835_bsc1
  • volatile uint32_t * bcm2835_aux
  • volatile uint32_t * bcm2835_spi1
  • volatile uint32_t * bcm2835_smi

💖 Detailed Description 💖

The values here are designed to be passed to various functions in the bcm2835 library. That's the whole tea ☕ — they're not decoration, they're the actual arguments these functions are expecting, so hand them over exactly as written 🫶

✨ Macro Definition Documentation ✨

okay bestie, here's the macro tea ☕ — every single #define in this section, same order, same values, no cap. 💅

  • #define BCM2835_AUX_BASE 0x215000 — Base Address of the AUX registers. the AUX home base 💖
  • #define BCM2835_AUX_ENABLE_SPI0 0x02 — SPI0 (SPI1 in the device). the naming is a whole situation, bestie ✨
  • #define BCM2835_AUX_ENABLE_SPI1 0x04 — SPI1 (SPI2 in the device). yes, another plot twist 🦋
  • #define BCM2835_AUX_IRQ 0x0000 — xxx. literally just xxx, iconic mystery energy 💀
  • #define BCM2835_AUX_SPI_CLOCK_MAX 125000000 — 125Mhz. fast queen 🔥
  • #define BCM2835_AUX_SPI_CLOCK_MIN 30500 — 30,5kHz. comma included, periodt 🍓
  • #define BCM2835_AUX_SPI_CNTL0_CS0_N 0x000C0000 — CS 0 low. grounded 🌸
  • #define BCM2835_AUX_SPI_CNTL0_CS1_N 0x000A0000 — CS 1 low. also grounded 🌸
  • #define BCM2835_AUX_SPI_CNTL0_CS2_N 0x00060000 — CS 2 low. still grounded 🌸
  • #define BCM2835_AUX_SPI_IO 0x0020 — Write = TX, read=RX. the duality of SPI 🫶
  • #define BCM2835_AUX_SPI_PEEK 0x000C — Read but do not take from FF. look but don't touch, respect 👑
  • #define BCM2835_AUX_SPI_TXHOLD 0x0030 — Write = TX keep CS, read=RX. hold that CS, bestie 💅
  • #define BCM2835_BLOCK_SIZE (4*1024) — Size of memory block on RPi. block party 🧚
  • #define BCM2835_BSC0_BASE 0x205000 — Base Address of the BSC0 registers. BSC0 base camp ⭐
  • #define BCM2835_BSC1_BASE 0x804000 — Base Address of the BSC1 registers. BSC1 base camp ⭐
  • #define BCM2835_BSC_A 0x000c — BSC Master Slave Address. address realness 🎀
  • #define BCM2835_BSC_C 0x0000 — BSC Master Control. control freak, but make it I2C 😭
  • #define BCM2835_BSC_C_CLEAR_1 0x00000020 — Clear FIFO Clear. clear the FIFO, clear the vibes 🧹
  • #define BCM2835_BSC_C_CLEAR_2 0x00000010 — Clear FIFO Clear. again, but different bit 🧹
  • #define BCM2835_BSC_C_I2CEN 0x00008000 — I2C Enable, 0 = disabled, 1 = enabled. turn it on or off, no in-between 🔥
  • #define BCM2835_BSC_C_INTD 0x00000100 — Interrupt on DONE. notify me when you're done, bestie 📣
  • #define BCM2835_BSC_C_INTR 0x00000400 — Interrupt on RX. RX interrupt glow ✨
  • #define BCM2835_BSC_C_INTT 0x00000200 — Interrupt on TX. TX interrupt glow ✨
  • #define BCM2835_BSC_C_READ 0x00000001 — Read transfer. read mode activated 📖
  • #define BCM2835_BSC_C_ST 0x00000080 — Start transfer, 1 = Start a new transfer. start the transfer, main character energy 👑
  • #define BCM2835_BSC_CLKT 0x001c — BSC Master Clock Stretch Timeout. timeout, but clock stretch edition 💀
  • #define BCM2835_BSC_DEL 0x0018 — BSC Master Data Delay. fashionably late data 🍓
  • #define BCM2835_BSC_DIV 0x0014 — BSC Master Clock Divider. divide and conquer 🧚
  • #define BCM2835_BSC_DLEN 0x0008 — BSC Master Data Length. length matters 💅
  • #define BCM2835_BSC_FIFO 0x0010 — BSC Master Data FIFO. FIFO is life 🦋
  • #define BCM2835_BSC_FIFO_SIZE 16 — BSC FIFO size. 16, slay ✨
  • #define BCM2835_BSC_S 0x0004 — BSC Master Status. status check 🫶
  • #define BCM2835_BSC_S_CLKT 0x00000200 — Clock stretch timeout. stretch, but make it timeout 😭
  • #define BCM2835_BSC_S_DONE 0x00000002 — Transfer DONE. DONE done, periodt 💖
  • #define BCM2835_BSC_S_ERR 0x00000100 — ACK error. error, we don't love that 💀
  • #define BCM2835_BSC_S_RXD 0x00000020 — RXD FIFO contains data. data detected 🌸
  • #define BCM2835_BSC_S_RXF 0x00000080 — RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full. full or not full, the binary tea ☕
  • #define BCM2835_BSC_S_RXR 0x00000008 — RXR FIFO needs reading (full). read me, I'm full 📖
  • #define BCM2835_BSC_S_TA 0x00000001 — Transfer Active. active transfer, main character 👑
  • #define BCM2835_BSC_S_TXD 0x00000010 — TXD FIFO can accept data. send it 📤
  • #define BCM2835_BSC_S_TXE 0x00000040 — TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full. full again, binary bestie ☕
  • #define BCM2835_BSC_S_TXW 0x00000004 — TXW FIFO needs writing (full). write me, I'm full ✍️
  • #define BCM2835_CLOCK_BASE 0x101000 — Base Address of the Clock/timer registers. clock base, tick tock 🕰️
  • #define BCM2835_CORE_CLK_HZ 250000000 — Speed of the core clock core_clk 250 MHz. 250 MHz, fast queen 🔥
  • #define BCM2835_GPAFEN0 0x0088 — GPIO Pin Async. Falling Edge Detect 0. falling edge, async era 🦋
  • #define BCM2835_GPAFEN1 0x008c — GPIO Pin Async. Falling Edge Detect 1. falling edge, take two 🦋
  • #define BCM2835_GPAREN0 0x007c — GPIO Pin Async. Rising Edge Detect 0. rising edge, async era 🌈
  • #define BCM2835_GPAREN1 0x0080 — GPIO Pin Async. Rising Edge Detect 1. rising edge, take two 🌈
  • #define BCM2835_GPCLR0 0x0028 — GPIO Pin Output Clear 0. clear it out 🧹
  • #define BCM2835_GPCLR1 0x002c — GPIO Pin Output Clear 1. clear it out again 🧹
  • #define BCM2835_GPEDS0 0x0040 — GPIO Pin Event Detect Status 0. event status, very gossip 👀
  • #define BCM2835_GPEDS1 0x0044 — GPIO Pin Event Detect Status 1. event status, part two 👀
  • #define BCM2835_GPFEN0 0x0058 — GPIO Pin Falling Edge Detect Enable 0. falling edge enable 🦋
  • #define BCM2835_GPFEN1 0x005c — GPIO Pin Falling Edge Detect Enable 1. falling edge enable, again 🦋
  • #define BCM2835_GPFSEL0 0x0000 — GPIO register offsets from BCM2835_GPIO_BASE. Offsets into the GPIO Peripheral block in bytes per 6.1 Register View GPIO Function Select 0. function select zero, the origin story ✨
  • #define BCM2835_GPFSEL1 0x0004 — GPIO Function Select 1. select one 💅
  • #define BCM2835_GPFSEL2 0x0008 — GPIO Function Select 2. select two 💅
  • #define BCM2835_GPFSEL3 0x000c — GPIO Function Select 3. select three 💅
  • #define BCM2835_GPFSEL4 0x0010 — GPIO Function Select 4. select four 💅
  • #define BCM2835_GPFSEL5 0x0014 — GPIO Function Select 5. select five, the finale 💅
  • #define BCM2835_GPHEN0 0x0064 — GPIO Pin High Detect Enable 0. high detect, enable ⭐
  • #define BCM2835_GPHEN1 0x0068 — GPIO Pin High Detect Enable 1. high detect, enable again ⭐
  • #define BCM2835_GPIO_BASE 0x200000 — Base Address of the GPIO registers. GPIO home base 🏠
  • #define BCM2835_GPIO_PADS 0x100000 — Base Address of the Pads registers. pads base, cute 🎀
  • #define BCM2835_GPIO_PWM 0x20C000 — Base Address of the PWM registers. PWM base, pulse width realness 🌈
  • #define BCM2835_GPLEN0 0x0070 — GPIO Pin Low Detect Enable 0. low detect enable 🦋
  • #define BCM2835_GPLEN1 0x0074 — GPIO Pin Low Detect Enable 1. low detect enable again 🦋
  • #define BCM2835_GPLEV0 0x0034 — GPIO Pin Level 0. level zero ✨
  • #define BCM2835_GPLEV1 0x0038 — GPIO Pin Level 1. level one ✨
  • #define BCM2835_GPPUD 0x0094 — GPIO Pin Pull-up/down Enable. pull up or pull down, choose your fighter 💅
  • #define BCM2835_GPPUDCLK0 0x0098 — GPIO Pin Pull-up/down Enable Clock 0. pull clock zero 🕰️
  • #define BCM2835_GPPUDCLK1 0x009c — GPIO Pin Pull-up/down Enable Clock 1. pull clock one 🕰️
  • #define BCM2835_GPREN0 0x004c — GPIO Pin Rising Edge Detect Enable 0. rising edge enable 🌈
  • #define BCM2835_GPREN1 0x0050 — GPIO Pin Rising Edge Detect Enable 1. rising edge enable again 🌈
  • #define BCM2835_GPSET0 0x001c — GPIO Pin Output Set 0. set it off 🔥
  • #define BCM2835_GPSET1 0x0020 — GPIO Pin Output Set 1. set it off again 🔥
  • #define BCM2835_PAD_DRIVE_10mA 0x04 — 10mA drive current. 10mA, strong 💪
  • #define BCM2835_PAD_DRIVE_12mA 0x05 — 12mA drive current. 12mA, stronger 💪
  • #define BCM2835_PAD_DRIVE_14mA 0x06 — 14mA drive current. 14mA, even stronger 💪
  • #define BCM2835_PAD_DRIVE_16mA 0x07 — 16mA drive current. 16mA, maximum slay 👑
  • #define BCM2835_PAD_DRIVE_2mA 0x00 — 2mA drive current. 2mA, soft launch 🌸
  • #define BCM2835_PAD_DRIVE_4mA 0x01 — 4mA drive current. 4mA, gentle 🌸
  • #define BCM2835_PAD_DRIVE_6mA 0x02 — 6mA drive current. 6mA, warming up 🌸
  • #define BCM2835_PAD_DRIVE_8mA 0x03 — 8mA drive current. 8mA, solid 🌸
  • #define BCM2835_PAD_HYSTERESIS_ENABLED 0x08 — Hysteresis enabled. hysteresis, enabled era 🦋
  • #define BCM2835_PAD_PASSWRD (0x5A << 24) — Pad Control masks Password to enable setting pad mask. password to the pad party 🔐
  • #define BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10 — Slew rate unlimited. unlimited slew, no limits 🔥
  • #define BCM2835_PADS_GPIO_0_27 0x002c — Pad control register offsets from BCM2835_GPIO_PADS Pad control register for pads 0 to 27. pads 0 to 27, represented 🎀
  • #define BCM2835_PADS_GPIO_28_45 0x0030 — Pad control register for pads 28 to 45. pads 28 to 45, represented 🎀
  • #define BCM2835_PADS_GPIO_46_53 0x0034 — Pad control register for pads 46 to 53. pads 46 to 53, represented 🎀
  • #define BCM2835_PAGE_SIZE (4*1024) — Size of memory page on RPi. page size, pageant winner 👑
  • #define BCM2835_PERI_BASE 0x20000000 — Physical addresses for various peripheral register sets Base Physical Address of the BCM 2835 peripheral registers Note this is different for the RPi2 BCM2836, where this is derived from /proc/device-tree/soc/ranges If /proc/device-tree/soc/ranges exists on a RPi 1 OS, it would be expected to contain the following numbers: Peripherals block base address on RPi 1. the base to rule them all, with lore 📜
  • #define BCM2835_PERI_SIZE 0x01000000 — Size of the peripherals block on RPi 1. big block energy 🧱
  • #define BCM2835_RPI2_PERI_BASE 0x3F000000 — Alternate base address for RPI 2 / 3. RPI 2 / 3 alternate base, iconic ✨
  • #define BCM2835_RPI4_PERI_BASE 0xFE000000 — Alternate base address for RPI 4. RPI 4 alternate base, newer icon ✨
  • #define BCM2835_RPI4_PERI_SIZE 0x01800000 — Alternate size for RPI 4. RPI 4 alternate size, big 🧱
  • #define BCM2835_SMI_BASE 0x600000 — Base address of the SMI registers. SMI base, hello 👋
  • #define BCM2835_SPI0_BASE 0x204000 — Base Address of the SPI0 registers. SPI0 base, the classic 💖
  • #define BCM2835_SPI0_CLK 0x0008 — SPI Master Clock Divider. SPI clock divider, math queen ➗
  • #define BCM2835_SPI0_CS 0x0000 — SPI Master Control and Status. control and status, multitasking 💅
  • #define BCM2835_SPI0_CS_ADCS 0x00000800 — ADCS Automatically Deassert Chip Select. auto deassert, independent 🦋
  • #define BCM2835_SPI0_CS_CLEAR 0x00000030 — Clear FIFO Clear RX and TX. clear RX and TX, full reset 🧹
  • #define BCM2835_SPI0_CS_CLEAR_RX 0x00000020 — Clear FIFO Clear RX. clear RX only 🧹
  • #define BCM2835_SPI0_CS_CLEAR_TX 0x00000010 — Clear FIFO Clear TX. clear TX only 🧹
  • #define BCM2835_SPI0_CS_CPHA 0x00000004 — Clock Phase. clock phase, phase one 🌙
  • #define BCM2835_SPI0_CS_CPOL 0x00000008 — Clock Polarity. clock polarity, polarity queen 🌈
  • #define BCM2835_SPI0_CS_CS 0x00000003 — Chip Select. chip select, choose me 👑
  • #define BCM2835_SPI0_CS_CSPOL 0x00000040 — Chip Select Polarity. chip select polarity 🦋
  • #define BCM2835_SPI0_CS_CSPOL0 0x00200000 — Chip Select 0 Polarity. chip select 0 polarity 🦋
  • #define BCM2835_SPI0_CS_CSPOL1 0x00400000 — Chip Select 1 Polarity. chip select 1 polarity 🦋
  • #define BCM2835_SPI0_CS_CSPOL2 0x00800000 — Chip Select 2 Polarity. chip select 2 polarity 🦋
  • #define BCM2835_SPI0_CS_DMA_LEN 0x01000000 — Enable DMA mode in Lossi mode. DMA mode, lossi mode crossover episode 🔥
  • #define BCM2835_SPI0_CS_DMAEN 0x00000100 — DMAEN DMA Enable. DMA enable, let's go 🚀
  • #define BCM2835_SPI0_CS_DONE 0x00010000 — Done transfer Done. done done, periodt 💅
  • #define BCM2835_SPI0_CS_INTD 0x00000200 — INTD Interrupt on Done. interrupt on done, notify me 📣
  • #define BCM2835_SPI0_CS_INTR 0x00000400 — INTR Interrupt on RXR. interrupt on RXR 📣
  • #define BCM2835_SPI0_CS_LEN 0x00002000 — LEN LoSSI enable. LoSSI enable, niche but valid 🦋
  • #define BCM2835_SPI0_CS_LEN_LONG 0x02000000 — Enable Long data word in Lossi mode if DMA_LEN is set. long data word, only if DMA_LEN is set — conditional queen 👑
  • #define BCM2835_SPI0_CS_LMONO 0x00004000 — Unused. unused, ghosted 💀
  • #define BCM2835_SPI0_CS_REN 0x00001000 — REN Read Enable. read enable, turn up 📖
  • #define BCM2835_SPI0_CS_RXD 0x00020000 — RXD RX FIFO contains Data. RX FIFO has data 📥
  • #define BCM2835_SPI0_CS_RXF 0x00100000 — RXF - RX FIFO Full. RX FIFO full, no more room 💀
  • #define BCM2835_SPI0_CS_RXR 0x00080000 — RXR RX FIFO needs Reading (full). RX FIFO needs reading, full situation 📖
  • #define BCM2835_SPI0_CS_TA 0x00000080 — Transfer Active. transfer active, main character 👑
  • #define BCM2835_SPI0_CS_TE_EN 0x00008000 — Unused. unused again, ghosted again 💀
  • #define BCM2835_SPI0_CS_TXD 0x00040000 — TXD TX FIFO can accept Data. TX FIFO can accept data 📤
  • #define BCM2835_SPI0_DC 0x0014 — SPI DMA DREQ Controls. DMA DREQ controls, fancy ✨
  • #define BCM2835_SPI0_DLEN 0x000c — SPI Master Data Length. data length, measure twice 📏
  • #define BCM2835_SPI0_FIFO 0x0004 — SPI Master TX and RX FIFOs. TX and RX FIFOs, the duo 🫶
  • #define BCM2835_SPI0_LTOH 0x0010 — SPI LOSSI mode TOH. LOSSI mode TOH, very specific 🎀
  • #define BCM2835_SPI1_BASE 0x215080 — Base Address of the AUX_SPI1 registers. AUX_SPI1 base, spin-off 💖
  • #define BCM2835_SPI2_BASE 0x2150C0 — Base Address of the AUX_SPI2 registers. AUX_SPI2 base, sequel 💖
  • #define BCM2835_ST_BASE 0x3000 — Offsets for the bases of various peripherals within the peripherals block / Base Address of the System Timer registers. system timer base, the clock keeper 🕰️
  • #define BCM2835_ST_CHI 0x0008 — System Timer Counter Upper 32 bits. upper 32 bits, high half ⬆️
  • #define BCM2835_ST_CLO 0x0004 — System Timer Counter Lower 32 bits. lower 32 bits, low half ⬇️
  • #define BCM2835_ST_CS 0x0000 — System Timer Control/Status. system timer control/status, dual threat 💅
  • #define BMC2835_RPI2_DT_FILENAME '/proc/device-tree/soc/ranges' — On all recent OSs, the base of the peripherals is read from a /proc file. read from a /proc file, very Unix of it 🐧
  • #define HIGH 0x1 — This means pin HIGH, true, 3.3volts on a pin. HIGH, true, 3.3 volts — turned up ⚡
  • #define LOW 0x0 — This means pin LOW, false, 0volts on a pin. LOW, false, 0 volts — grounded 🌊
  • #define MIN(a, b) (a < b ? a : b) — Return the minimum of 2 numbers. minimum of 2 numbers, tiny but mighty 🧚

✨ Enumeration Type Documentation ✨

okay so enum bcm2835FunctionSelect is giving port function realness ✨

bcm2835PortFunction Port function select modes for bcm2835_gpio_fsel(). 💅

Enumerator 🫶

  • BCM2835_GPIO_FSEL_INPT — Input 0b000. input mode, listening era 👂
  • BCM2835_GPIO_FSEL_OUTP — Output 0b001. output mode, speaking era 📣
  • BCM2835_GPIO_FSEL_ALT0 — Alternate function 0 0b100. alt 0, the original alternate 🦋
  • BCM2835_GPIO_FSEL_ALT1 — Alternate function 1 0b101. alt 1, the sequel 🦋
  • BCM2835_GPIO_FSEL_ALT2 — Alternate function 2 0b110,. alt 2, comma included, periodt 💖
  • BCM2835_GPIO_FSEL_ALT3 — Alternate function 3 0b111. alt 3, trilogy energy 🦋
  • BCM2835_GPIO_FSEL_ALT4 — Alternate function 4 0b011. alt 4, unexpected but iconic 🦋
  • BCM2835_GPIO_FSEL_ALT5 — Alternate function 5 0b010. alt 5, the finale 🦋

BCM2835_GPIO_FSEL_MASK — the mask for the function-select bits, and it's 0b111 bestie, three whole bits 💅

🌸 enum bcm2835I2CClockDivider 🌸

bcm2835I2CClockDivider is the divider situation used to generate the I2C clock from the system clock. The clock divided is based on a nominal base clock rate of 250MHz. Slay. ✨

Enumerator:

  • BCM2835_I2C_CLOCK_DIVIDER_2500 — 2500 = 10us = 100 kHz 🐌
  • BCM2835_I2C_CLOCK_DIVIDER_626 — 622 = 2.504us = 399.3610 kHz
  • BCM2835_I2C_CLOCK_DIVIDER_150 — 150 = 60ns = 1.666 MHz (this is the default at reset, no cap)
  • BCM2835_I2C_CLOCK_DIVIDER_148 — 148 = 59ns = 1.689 MHz 🏎️

💖 enum bcm2835I2CReasonCodes 💖

bcm2835I2CReasonCodes — the reason codes that bcm2835_i2c_write and bcm2835_i2c_read hand you back. It's giving "explain yourself" energy fr fr.

Enumerator:

  • BCM2835_I2C_REASON_OK — Success 🎉 (the one you actually want)
  • BCM2835_I2C_REASON_ERROR_NACK — received a NACK 😭
  • BCM2835_I2C_REASON_ERROR_CLKT — received Clock Stretch Timeout
  • BCM2835_I2C_REASON_ERROR_DATA — not all data is sent / received 💀
  • BCM2835_I2C_REASON_ERROR_TIMEOUT — a time out occurred during sending

🦋 enum bcm2835PadGroup 🦋

bcm2835PadGroup — the pad group specification for bcm2835_gpio_pad(). Pads got groups now, iconic.

Enumerator:

  • BCM2835_PAD_GROUP_GPIO_0_27 — pad group for GPIO pads 0 to 27
  • BCM2835_PAD_GROUP_GPIO_28_45 — pad group for GPIO pads 28 to 45
  • BCM2835_PAD_GROUP_GPIO_46_53 — pad group for GPIO pads 46 to 53

🎀 enum bcm2835PUDControl 🎀

bcm2835PUDControl — the pullup/pulldown defines for bcm2835_gpio_pud(). Little binary values, adorable.

Enumerator:

  • BCM2835_GPIO_PUD_OFF — Off ? disable pull-up/down 0b00 (yes, the question mark is canon, I don't make the rules 🙈)
  • BCM2835_GPIO_PUD_DOWN — enable Pull Down control 0b01
  • BCM2835_GPIO_PUD_UP — enable Pull Up control 0b10 ⬆️

🌈 enum bcm2835RegisterBase 🌈

bcm2835RegisterBase — the register bases you feed to bcm2835_regbase(). Pick your fighter:

Enumerator:

  • BCM2835_REGBASE_ST — base of the ST (System Timer) registers.
  • BCM2835_REGBASE_GPIO — base of the GPIO registers.
  • BCM2835_REGBASE_PWM — base of the PWM registers.
  • BCM2835_REGBASE_CLK — base of the CLK registers.
  • BCM2835_REGBASE_PADS — base of the PADS registers.
  • BCM2835_REGBASE_SPI0 — base of the SPI0 registers.
  • BCM2835_REGBASE_BSC0 — base of the BSC0 registers.
  • BCM2835_REGBASE_BSC1 — base of the BSC1 registers.
  • BCM2835_REGBASE_AUX — base of the AUX registers.
  • BCM2835_REGBASE_SPI1 — base of the SPI1 registers.
  • BCM2835_REGBASE_SMI — base of the SMI registers.

⭐ enum bcm2835SPIBitOrder ⭐

bcm2835SPIBitOrder — SPI bit order. Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder(). Which end of the bits goes first, basically.

Enumerator:

  • BCM2835_SPI_BIT_ORDER_LSBFIRST — LSB First
  • BCM2835_SPI_BIT_ORDER_MSBFIRST — MSB First 👑

💜 enum bcm2835SPIChipSelect 💜

bcm2835SPIChipSelect — specify the SPI chip select pin(s). Choose your chip bestie.

Enumerator:

  • BCM2835_SPI_CS0 — Chip Select 0
  • BCM2835_SPI_CS1 — Chip Select 1
  • BCM2835_SPI_CS2 — Chip Select 2 (ie pins CS1 and CS2 are asserted) 👀
  • BCM2835_SPI_CS_NONE — no CS, control it yourself. Main character move, honestly. 🫶

🔥 enum bcm2835SPIClockDivider 🔥

bcm2835SPIClockDivider — the divider used to generate the SPI clock from the system clock. The figures below give the divider, clock period and clock frequency. Clock divided is based on a nominal core clock rate of 250MHz on RPi1 and RPi2, and 400MHz on RPi3.

It is reported that (contrary to the documentation) any even divider may be used. 🫣

The frequencies shown for each divider have been confirmed by measurement on RPi1 and RPi2. The system clock frequency on RPi3 is different, so the frequency you get from a given divider will be different. See comments in 'SPI Pins' for information about reliable SPI speeds.

Note: it is possible to change the core clock rate of the RPi 3 back to 250MHz, by putting

core_freq=250

in the config.txt ✨

Enumerator:

  • BCM2835_SPI_CLOCK_DIVIDER_65536 — 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_32768 — 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_16384 — 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_8192 — 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_4096 — 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_2048 — 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_1024 — 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_512 — 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_256 — 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_128 — 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_64 — 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_32 — 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_16 — 16 = 15.625MHz on Rpi2, 25MHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_8 — 8 = 31.25MHz on Rpi2, 50MHz on RPI3
  • BCM2835_SPI_CLOCK_DIVIDER_4 — 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. 💀
  • BCM2835_SPI_CLOCK_DIVIDER_2 — 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably. 💀💀
  • BCM2835_SPI_CLOCK_DIVIDER_1 — 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536

🧚 enum bcm2835SPIMode 🧚

SPI Data mode — specify the SPI data mode to be passed to bcm2835_spi_setDataMode(). CPOL and CPHA, the iconic duo.

Enumerator:

  • BCM2835_SPI_MODE0 — CPOL = 0, CPHA = 0
  • BCM2835_SPI_MODE1 — CPOL = 0, CPHA = 1
  • BCM2835_SPI_MODE2 — CPOL = 1, CPHA = 0
  • BCM2835_SPI_MODE3 — CPOL = 1, CPHA = 1

👑 enum RPiGPIOPin 👑

GPIO Pin Numbers, bestie. Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers. These can be passed as a pin number to any function requiring a pin.

Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins and some can adopt an alternate function. RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*. RPi B+ has yet differnet pinouts and these are defined in RPI_BPLUS_*. ⚠️

At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively. When SPI0 is in use (ie after bcm2835_spi_begin()), SPI0 pins are dedicated to SPI and cant be controlled independently.

If you are using the RPi Compute Module, just use the GPIO number: there is no need to use one of these symbolic names. 🫶

Enumerator:

  • RPI_GPIO_P1_03 — Version 1, Pin P1-03
  • RPI_GPIO_P1_05 — Version 1, Pin P1-05
  • RPI_GPIO_P1_07 — Version 1, Pin P1-07
  • RPI_GPIO_P1_08 — Version 1, Pin P1-08, defaults to alt function 0 UART0_TXD
  • RPI_GPIO_P1_10 — Version 1, Pin P1-10, defaults to alt function 0 UART0_RXD
  • RPI_GPIO_P1_11 — Version 1, Pin P1-11
  • RPI_GPIO_P1_12 — Version 1, Pin P1-12, can be PWM channel 0 in ALT FUN 5
  • RPI_GPIO_P1_13 — Version 1, Pin P1-13
  • RPI_GPIO_P1_15 — Version 1, Pin P1-15
  • RPI_GPIO_P1_16 — Version 1, Pin P1-16
  • RPI_GPIO_P1_18 — Version 1, Pin P1-18
  • RPI_GPIO_P1_19 — Version 1, Pin P1-19, MOSI when SPI0 in use
  • RPI_GPIO_P1_21 — Version 1, Pin P1-21, MISO when SPI0 in use
  • RPI_GPIO_P1_22 — Version 1, Pin P1-22
  • RPI_GPIO_P1_23 — Version 1, Pin P1-23, CLK when SPI0 in use
  • RPI_GPIO_P1_24 — Version 1, Pin P1-24, CE0 when SPI0 in use
  • RPI_GPIO_P1_26 — Version 1, Pin P1-26, CE1 when SPI0 in use
  • RPI_V2_GPIO_P1_03 — Version 2, Pin P1-03
  • RPI_V2_GPIO_P1_05 — Version 2, Pin P1-05
  • RPI_V2_GPIO_P1_07 — Version 2, Pin P1-07
  • RPI_V2_GPIO_P1_08 — Version 2, Pin P1-08, defaults to alt function 0 UART0_TXD
  • RPI_V2_GPIO_P1_10 — Version 2, Pin P1-10, defaults to alt function 0 UART0_RXD
  • RPI_V2_GPIO_P1_11 — Version 2, Pin P1-11
  • RPI_V2_GPIO_P1_12 — Version 2, Pin P1-12, can be PWM channel 0 in ALT FUN 5
  • RPI_V2_GPIO_P1_13 — Version 2, Pin P1-13
  • RPI_V2_GPIO_P1_15 — Version 2, Pin P1-15
  • RPI_V2_GPIO_P1_16 — Version 2, Pin P1-16
  • RPI_V2_GPIO_P1_18 — Version 2, Pin P1-18
  • RPI_V2_GPIO_P1_19 — Version 2, Pin P1-19, MOSI when SPI0 in use
  • RPI_V2_GPIO_P1_21 — Version 2, Pin P1-21, MISO when SPI0 in use
  • RPI_V2_GPIO_P1_22 — Version 2, Pin P1-22
  • RPI_V2_GPIO_P1_23 — Version 2, Pin P1-23, CLK when SPI0 in use
  • RPI_V2_GPIO_P1_24 — Version 2, Pin P1-24, CE0 when SPI0 in use
  • RPI_V2_GPIO_P1_26 — Version 2, Pin P1-26, CE1 when SPI0 in use
  • RPI_V2_GPIO_P1_29 — Version 2, Pin P1-29
  • RPI_V2_GPIO_P1_31 — Version 2, Pin P1-31
  • RPI_V2_GPIO_P1_32 — Version 2, Pin P1-32
  • RPI_V2_GPIO_P1_33 — Version 2, Pin P1-33
  • RPI_V2_GPIO_P1_35 — Version 2, Pin P1-35, can be PWM channel 1 in ALT FUN 5
  • RPI_V2_GPIO_P1_36 — Version 2, Pin P1-36
  • RPI_V2_GPIO_P1_37 — Version 2, Pin P1-37
  • RPI_V2_GPIO_P1_38 — Version 2, Pin P1-38
  • RPI_V2_GPIO_P1_40 — Version 2, Pin P1-40
  • RPI_V2_GPIO_P5_03 — Version 2, Pin P5-03
  • RPI_V2_GPIO_P5_04 — Version 2, Pin P5-04
  • RPI_V2_GPIO_P5_05 — Version 2, Pin P5-05
  • RPI_V2_GPIO_P5_06 — Version 2, Pin P5-06
  • RPI_BPLUS_GPIO_J8_03 — B+, Pin J8-03
  • RPI_BPLUS_GPIO_J8_05 — B+, Pin J8-05
  • RPI_BPLUS_GPIO_J8_07 — B+, Pin J8-07
  • RPI_BPLUS_GPIO_J8_08 — B+, Pin J8-08, defaults to alt function 0 UART0_TXD
  • RPI_BPLUS_GPIO_J8_10 — B+, Pin J8-10, defaults to alt function 0 UART0_RXD
  • RPI_BPLUS_GPIO_J8_11 — B+, Pin J8-11
  • RPI_BPLUS_GPIO_J8_12 — B+, Pin J8-12, can be PWM channel 0 in ALT FUN 5
  • RPI_BPLUS_GPIO_J8_13 — B+, Pin J8-13
  • RPI_BPLUS_GPIO_J8_15 — B+, Pin J8-15
  • RPI_BPLUS_GPIO_J8_16 — B+, Pin J8-16
  • RPI_BPLUS_GPIO_J8_18 — B+, Pin J8-18
  • RPI_BPLUS_GPIO_J8_19 — B+, Pin J8-19, MOSI when SPI0 in use
  • RPI_BPLUS_GPIO_J8_21 — B+, Pin J8-21, MISO when SPI0 in use
  • RPI_BPLUS_GPIO_J8_22 — B+, Pin J8-22
  • RPI_BPLUS_GPIO_J8_23 — B+, Pin J8-23, CLK when SPI0 in use
  • RPI_BPLUS_GPIO_J8_24 — B+, Pin J8-24, CE0 when SPI0 in use
  • RPI_BPLUS_GPIO_J8_26 — B+, Pin J8-26, CE1 when SPI0 in use
  • RPI_BPLUS_GPIO_J8_29 — B+, Pin J8-29,
  • RPI_BPLUS_GPIO_J8_31 — B+, Pin J8-31
  • RPI_BPLUS_GPIO_J8_32 — B+, Pin J8-32
  • RPI_BPLUS_GPIO_J8_33 — B+, Pin J8-33
  • RPI_BPLUS_GPIO_J8_35 — B+, Pin J8-35, and fun fact: this one can be PWM channel 1 in ALT FUN 5 💅
  • RPI_BPLUS_GPIO_J8_36 — B+, Pin J8-36
  • RPI_BPLUS_GPIO_J8_37 — B+, Pin J8-37
  • RPI_BPLUS_GPIO_J8_38 — B+, Pin J8-38
  • RPI_BPLUS_GPIO_J8_40 — B+, Pin J8-40

🫶 Variable Documentation 🫶

okay bestie, this is the part where we meet the actual global variables ✨ these are the [extern] legends you get to poke at from your own code. Let's go, one by one 👑

volatile uint32_t* bcm2835_aux [extern]

Base of the AUX registers. This one only shows up after bcm2835_init has been called — as root, no cap 👑

volatile uint32_t* bcm2835_bsc0 [extern]

Base of the BSC0 registers. Available after bcm2835_init has been called (as root) 💖

volatile uint32_t* bcm2835_bsc1 [extern]

Base of the BSC1 registers. Available after bcm2835_init has been called (as root) 💖

volatile uint32_t* bcm2835_clk [extern]

Base of the CLK registers. Available after bcm2835_init has been called (as root) ⏰

volatile uint32_t* bcm2835_gpio [extern]

Base of the GPIO registers. Available after bcm2835_init has been called. (no root energy required on this one, bestie — she's the chill one) 🌸

volatile uint32_t* bcm2835_pads [extern]

Base of the PADS registers. Available after bcm2835_init has been called (as root) 💅

uint32_t* bcm2835_peripherals [extern]

The virtual memory address of the mapped peripherals block. Virtual, not physical — she lives in your process's little dream world 🌈

off_t bcm2835_peripherals_base [extern]

Physical address and size of the peripherals block. May be overridden on RPi2 — so don't you dare hardcode her fr fr 🙈

size_t bcm2835_peripherals_size [extern]

Size of the peripherals block that's gonna get mapped 📏

volatile uint32_t* bcm2835_pwm [extern]

Base of the PWM registers. Available after bcm2835_init has been called (as root) 🎀

volatile uint32_t* bcm2835_smi [extern]

Base of SMI registers. Available after bcm2835_init has been called (as root) ✨

volatile uint32_t* bcm2835_spi0 [extern]

Base of the SPI0 registers. Available after bcm2835_init has been called (as root) 🦋

volatile uint32_t* bcm2835_spi1 [extern]

Base of the SPI1 registers. Available after bcm2835_init has been called (as root) 🦋

volatile uint32_t* bcm2835_st [extern]

Base of the ST (System Timer) registers. Available after bcm2835_init has been called (as root) ⏱️

ngl the pattern here is so satisfying — nearly all of these are just "call bcm2835_init as root first, then she's yours" 💖 bcm2835_gpio is the icon who skips the root requirement, and bcm2835_peripherals, bcm2835_peripherals_base and bcm2835_peripherals_size are doing their own whole thing 🫶

👑 Author 👑

Generated automatically by Doxygen for bcm2835 straight from the source code. Not a human wrote this, bestie — the robot did it and honestly she ate 💅✨

aaaand that's the whole page, you made it to the end!! 🎉 this was bcm2835, Version 1.75, and you've been reading constants(3). go forth and poke at registers responsibly, ily, bye bestie 💖🦋🎀

📦 where this page comes from