__riscv_flush_icache(3)
β¨ __riscv_flush_icache β¨
okay bestie so you're on RISC-V, you just wrote some new instructions into memory, and now you need the instruction cache to actually know about it?? yeah. that's this. this is the <pink>Library Functions Manual</pink> page for __riscv_flush_icache(3), and it's lowkey iconic for anyone doing JITs, self-modifying code, or honestly just vibing too close to the metal. π
πΈ NAME πΈ
__riscv_flush_icache β flush icaches on RISC-V π§Ήβ¨
π LIBRARY π
Standard C library (libc, -lc) β she lives in libc, no cap. π«Ά
π¦ SYNOPSIS π¦
#include <sys/cachectl.h>
int __riscv_flush_icache(void *start, void *end, unsigned long flags);
π DESCRIPTION π
so like. __riscv_flush_icache() enforces ordering between stores and instruction cache fetches. that's the whole job. the way that stores and icache fetches need to be ordered, and this function is the one making it happen. π₯
the range of addresses over which ordering is enforced? that's specified by start and end. cute, right? you tell it where and it handles the rest. π
the flags argument controls the extent of this ordering. default behavior β meaning a flags value of 0 β is to enforce the fence on all threads in the current process. everyone gets the memo, periodt. π
setting the SYS_RISCV_FLUSH_ICACHE_LOCAL bit lets users indicate that enforcing ordering on only the current thread is necessary. so if you're feeling local, that's your girl. all other bits in flags are reserved β do not touch, do not pass go, don't even look at them funny. π
π STANDARDS π
Linux on RISC-V. that's the whole vibe check. β
π HISTORY π
- Linux 4.15 π°οΈ
- glibc 2.27 π°οΈ
she's been around a minute. a classic. a legend, even.
π SEE ALSO π
okay that's the page bestie, go flush those icaches, stay ordered, and remember: reserved bits are reserved for a reason π
this was Linux man-pages 6.20, dated 2026-02-08 β pages written with love (and a little chaos), mwah ππ
π¦ where this page comes from
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