OPENSSL_RISCVCAP(3ossl)

💅 OPENSSL_RISCVCAP — the RISC-V processor capabilities vector

okay bestie, this is OPENSSL_riscvcap from the 3ossl manual set, and it's literally all about telling libcrypto which RISC-V instruction set extensions your CPU is allowed to flex. no cap, it's giving "vibe check for your silicon" ✨

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🌸 SYNOPSIS 🌸

env OPENSSL_riscvcap=... <application>

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🎀 DESCRIPTION 🎀

so libcrypto fully supports RISC-V instruction set extensions — each one gets its own lil name in the capabilities vector. 🦋

on Linux, the moment libcrypto initializes, whatever the RISC-V Hardware Probing syscall (hwprobe) hands back gets stashed in that vector. on any other platform? everything's disabled, sorry babe. 💀

want to override which instructions your app gets to use? slay, just set the OPENSSL_riscvcap environment variable before you launch the application. 🫶

the env var is basically the RISC-V ISA string from the RISC-V Instruction Set Manual — and it's case insensitive, ngl that's a nice touch. BUT (and this is the important part 🙈) the environment variable parser inside libcrypto is lowkey limited, so every extension has to be prefixed with an underscore to even be recognizable. yes, this applies to the Vector extension too. periodt.

OPENSSL_riscvcap="rv64gc_v_zba_zbb_zbs..."

⚠️ heads up: extension implication is currently not implemented. so if you throw "rv64gc_b" at it, zba/zbb/zbs will not be implied in the capability vector. it does not do the math for you, bestie. 😭

✨ the extensions that are actually recognized rn ✨

• ZBA — Address Generation. Could be detected using hwprobe for Linux kernel >= 6.5 👑
• ZBB — Basic bit-manipulation. Could be detected using hwprobe for Linux kernel >= 6.5 👑
• ZBC — Carry-less multiplication. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZBS — Single-bit instructions. Could be detected using hwprobe for Linux kernel >= 6.5 👑
• ZBKB — Bit-manipulation for Cryptography. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZBKC — Carry-less multiplication for Cryptography. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZBKX — Crossbar permutations. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZKND — NIST Suite: AES Decryption. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZKNE — NIST Suite: AES Encryption. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZKNH — NIST Suite: Hash Function Instructions. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZKSED — ShangMi Suite: SM4 Block Cipher Instructions. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZKSH — ShangMi Suite: SM3 Hash Function Instructions. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZKR — Entropy Source Extension. (no kernel note on this one, that's just how it is 💅)
• ZKT — Data Independent Execution Latency. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• V — Vector Extension for Application Processors. Could be detected using hwprobe for Linux kernel >= 6.5 👑
• ZVBB — Vector Basic Bit-manipulation. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVBC — Vector Carryless Multiplication. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVKB — Vector Cryptography Bit-manipulation. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVKG — Vector GCM/GMAC. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVKNED — NIST Suite: Vector AES Block Cipher. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVKNHA — NIST Suite: Vector SHA-2 Secure Hash. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVKNHB — NIST Suite: Vector SHA-2 Secure Hash. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVKSED — ShangMi Suite: SM4 Block Cipher. Could be detected using hwprobe for Linux kernel >= 6.8 👑
• ZVKSH — ShangMi Suite: SM3 Secure Hash. Could be detected using hwprobe for Linux kernel >= 6.8 👑

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🌈 RETURN VALUES 🌈

not available, bestie. nothing to return. 🤷‍♀️

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💖 EXAMPLES 💖

check what capabilities are currently detected — literal main character energy:

$ openssl info -cpusettings
OPENSSL_riscvcap=RV64GC_ZBA_ZBB_ZBC_ZBS_V vlen:256

📌 note: the first word in the displayed capabilities is the RISC-V base architecture value, which comes from the compiler configuration — so it is not overridable by the environment variable, fr fr. and when the V extension is given, the riscv_vlen value is always displayed; there's no way to override riscv_vlen via the environment variable either. 🙅‍♀️

disable all instruction set extensions (yes, all of them, chaos mode):

export OPENSSL_riscvcap="rv64gc"

only enable the vector extension (minimalist queen 🎀):

export OPENSSL_riscvcap="rv64gc_v"

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👑 COPYRIGHT 👑

Copyright 2024 The OpenSSL Project Authors. All Rights Reserved.

Licensed under the Apache License 2.0 (the "License"). You may not use this file except in compliance with the License. You can obtain a copy in the file LICENSE in the source distribution or at <https://www.openssl.org/source/license.html>.

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okay that's the whole page, you ate that 💅 this was OpenSSL 3.5.6, dated 2026-04-07, and you can find it chilling under OPENSSL_RISCVCAP(3ossl) in section 3ossl. mwah 🫶✨