MOKA(1)

💖 MOKA — the model checker ancestor, but make it a vibe 💖

okay bestie, gather round, because this is moka from the CAO-VLSI Reference Manual (section 1 of the manual pages, if you're keeping track 🎀), and she is literally a CTL model checker. yes. the whole thing. let's go 💅

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✨ ORIGIN ✨

so this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France. 🇫🇷 iconic academic royalty, no cap.

• Web: http://asim.lip6.fr/recherche/alliance/
• E-mail: alliance-users@asim.lip6.fr

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🌸 SYNOPSIS 🌸

moka [-VDB] fsm_filename ctl_filename

that's it. that's the whole summoning ritual. two files, three optional letters, go off queen 🫶

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💫 DESCRIPTION 💫

moka is a CTL model checker. periodt.

She's made to run on FSM or RTL descriptions, and she supports the same VHDL subset as syf or boom — for the deets on that subset, go peek at SYF(1), BOOM(1), FSM(5), VBE(5). 📚

But — and this is the part where I hold your hand — moka imposes that:

• each register of the behavioral description has the same clock condition
• there are no tristate or multiplexed buses

in particular, the VHDL types MUX_BIT and WOR_BIT aren't not supported (yes, that's how the original says it, and honestly? relatable, she said what she said 💀).

so here's the pipeline, step by step, main character energy only:

1. First of all, moka builds the function transition of the FSM using a Reduced Ordered Binary Decision Diagrams representation. 🧠
2. Then she applies the initial conditions to find the first state (that's the INITIAL and/or RESET_COND keyword in the CTL(5) file format).
3. After that, she computes a symbolic simulation of the FSM to find all the reachable states. This computation takes into account the assumptions conditions (the ASSUME keyword in the CTL(5) file format).
4. And finally, moka verifies one by one each CTL formula. (see CTL(5) for the CTL file format details ✨)

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🔥 CTL OPERATORS 🔥

For each CTL sub-expression, moka will return the set of states that verifies the formula. For example, EX(p) will return the set of reachable states that verifies EX(p). she's thorough like that. 💅

the CTL operators, served fresh:

• EX(p) — returns all states which have almost one primary state successor that verifies p.
• EU(p,q) — returns all states that are the root of almost one path, such that p is true until q is always true.
• EG(p) — returns all states that are the root of almost one path, such that p is always true.
• AX(p) — returns all states which have all their primary state successor that verifies p.
• AU(p,q) — returns all states that are the root of only pathes from which p is true until q is always true.
• AG(p) — returns all states that are the root of only pathes, such that p is always true.

(yes, "pathes." she's French, she's doing her best, we love her for it 😭💖)

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🌈 ENVIRONMENT VARIABLES 🌈

• MBK_WORK_LIB — gives the path for the description and the CTL file. The default value is the current directory.
• MBK_CATA_LIB — gives some auxiliary pathes for the descriptions and the CTL file. The default value is the current directory.

set them, bestie. don't make her hunt for your files 🧚

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👑 OPTIONS 👑

• -V — Sets verbose mode on. Each step of the model checking is displayed on the standard output.
• -D — Sets debug mode on. Each step of the model checking is detailed on the standard output. In particular, all states set are displayed for each CTL sub-expression.
• -B — The input file is a VHDL description using the Alliance VHDL subset (see VBE(5) file format).

ngl -D is a lot of output. it's giving "she's telling you everything." you've been warned 💀

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🦋 FSM EXAMPLE 🦋

-- A multi fsm example

ENTITY example is
PORT
(
   ck       : in  BIT;
   data_in  : in  BIT;
   reset    : in  BIT;
   data_out : out BIT
);
END example;

ARCHITECTURE FSM OF example is

   TYPE A_ETAT_TYPE IS (A_E0, A_E1);
   SIGNAL A_NS, A_CS : A_ETAT_TYPE;

   TYPE B_ETAT_TYPE IS (B_E0, B_E1);
   SIGNAL B_NS, B_CS : B_ETAT_TYPE;

--PRAGMA CURRENT_STATE A_CS  FSM_A
--PRAGMA NEXT_STATE A_NS     FSM_A
--PRAGMA CLOCK ck            FSM_A
--PRAGMA FIRST_STATE A_E0    FSM_A

--PRAGMA CURRENT_STATE B_CS  FSM_B
--PRAGMA NEXT_STATE B_NS     FSM_B
--PRAGMA CLOCK ck            FSM_B
--PRAGMA FIRST_STATE B_E0    FSM_B

   SIGNAL ACK, REQ, DATA_INT : BIT;

BEGIN

A_1 : PROCESS ( A_CS, ACK )
BEGIN
  IF ( reset = '1' )
  THEN A_NS     <= A_E0;
       DATA_OUT <= '0';
       REQ      <= '0';
  ELSE
  CASE A_CS is
    WHEN A_E0 =>
      IF ( ACK ='1') THEN A_NS <= A_E1;
                     ELSE A_NS <= A_E0;
      END IF;
      DATA_OUT <= '0';
      REQ      <= '1';
    WHEN A_E1 =>
      IF ( ACK ='1') THEN A_NS <= A_E1;
                     ELSE A_NS <= A_E0;
      END IF;
      DATA_OUT <= DATA_INT;
      REQ      <= '0';
  END CASE;
  END IF;
END PROCESS A_1;

A_2 : PROCESS( ck )
BEGIN
    IF ( ck = '1' AND NOT ck'STABLE )
    THEN A_CS <= A_NS;
    END IF;
END PROCESS A_2;

-------

B_1 : PROCESS ( B_CS, ACK )
BEGIN
  IF ( reset = '1' )
  THEN B_NS     <= B_E0;
       DATA_INT <= '0';
       ACK      <= '0';
  ELSE
  CASE B_CS is
    WHEN B_E0 =>
      IF ( REQ ='1') THEN B_NS <= B_E1;
                     ELSE B_NS <= B_E0;
      END IF;
      DATA_INT <= '0';
      ACK      <= '0';
    WHEN B_E1 =>
      IF ( REQ ='1') THEN B_NS <= B_E1;
                     ELSE B_NS <= B_E0;
      END IF;
      DATA_INT <= DATA_IN;
      ACK      <= '1';
  END CASE;
  END IF;
END PROCESS B_1;

B_2 : PROCESS( ck )
BEGIN
    IF ( ck = '1' AND NOT ck'STABLE )
    THEN B_CS <= B_NS;
    END IF;
END PROCESS B_2;

END FSM;

look at those --PRAGMA lines. that's how she knows which signal is the current state, which is the next state, which is the clock, and which is the first state. slay ✨

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💜 CTL EXAMPLE 💜

-- A CTL file example

   TYPE A_ETAT_TYPE IS (A_E0, A_E1);
   TYPE B_ETAT_TYPE IS (B_E0, B_E1);

   VARIABLE A_NS, A_CS : A_ETAT_TYPE;
   VARIABLE B_NS, B_CS : B_ETAT_TYPE;

   VARIABLE    ck       : BIT;
   VARIABLE    data_in  : BIT;
   VARIABLE    data_out : BIT;
   VARIABLE    reset    : BIT;
   VARIABLE    ack      : BIT;
   VARIABLE    req      : BIT;

   RESET_COND init1 := (reset='1');
   ASSUME     ass1  := (reset='0');

begin

       prop1 : EX( ack='1' );
       prop2 : AG( req -> AF( ack ) );
       prop4 : AU( req='1', ack='1');

end;

see RESET_COND and ASSUME in there? that's the initial conditions and the assumptions from the description up above. it all connects, iykyk 🔗

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⭐ MOKA EXAMPLE ⭐

     moka -V example example

verbose mode, FSM file, CTL file. two examples because that's the name she was given. go bestie go 🎀

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🍓 SEE ALSO 🍓

syf (1), fsp (1), fsm (5), ctl (5), vbe(5).

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💀 BUG REPORT 💀

This tool is under development at the ASIM department of the LIP6 laboratory.

We need your feedback to improve documentation and tools. 🫶 (fr fr, tell them things. they're asking nicely.)

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and that's the whole page, bestie!! this was the MOKA(1) page from the ASIM/LIP6 crew, dated August 5, 2002 — a classic, an icon, a legend. now go model-check something and make her proud 💖✨🌸🦋💅👑