ASIMUT(1)

📦 version 5.1.1, in fedora 43, fedora 44

💖 asimut(1) — the cao-vlsi reference manual, bestie edition 💖

okay so. hi. welcome to asimut(1), from the cao-vlsi reference manual. this is the whole page, every flag, every env var, nothing skipped, and i'm gonna make it make sense. grab a strawberry 🍓 and let's go.

✨ NAME ✨

asimut — a simulation tool for hardware descriptions. yes literally that's it, that's the whole vibe.

🌸 ORIGIN 🌸

this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France. 🇫🇷 iconic honestly.

🎀 SYNOPSIS 🎀

asimut [options] [root_file] [pattern_file] [result_file]

that's the whole shape of it. options first, then your three files if you want them.

👑 DESCRIPTION 👑

so asimut is a logical simulation tool for hardware descriptions. it compiles and loads a complete hardware description written in VHDL (Very high speed integrated circuits Hardware Description Language — say that five times fast, i dare you 💀).

the hardware description can be either:

  • structural — a hierarchy of instances, or
  • behavioural
⚠️ but here's the tea: only a subset of VHDL is supported. descriptions that don't match this subset cause a syntax error during compilation. if you wanna know exactly which subset is supported, go read vhdl(5). that's the one with the details, not me.

once a hardware description is loaded, asimut goes looking for a simulation pattern description file. this file is written in pat format. it gets compiled, loaded, and linked with the hardware description. then the simulation starts. and when the patterns are processed, a result file in pat format comes out the other side. ✨

if a save action has been requested in the pattern description file (peep pat(5) for that), asimut also creates a save file representing the state of the description at the end of the simulation of the last pattern. that save file is named root_file.sav, where root_file is the name of the description.

and what's the save file for? bestie it's for time travel (kind of). you can use it in a later simulation sequence to initialize the state of the (same) hardware description before the simulation begins. using this mechanism, a large sequence of patterns can be breaked onto several small sequences — each one initializing the hardware description with the save file resulted from the previous sequence. 🦋

asimut also reads several parameters from the environment variables:

  • MBK_CATA_LIB — list of directories containing description and pattern files (using $PATH syntax). The default path is the current directory (see mbk(1)).
  • MBK_WORK_LIB — specifies the current working directory. The working directory indicates the place where all output files are written.
  • MBK_CATAL_NAME — Indicates the file where the behavioral description files are listed. This file is used to leaf cells of a structural description. (see mbk(1))
  • MBK_IN_LO — file extension for structural entity. (see mbk(1))
  • VH_BEHSFX — list of file extensions for behavioural entities (using $PATH syntax). The default file extension is vbe.
  • VH_PATSFX — list of file extensions for pattern description entities (using $PATH syntax). The default file extension is pat.
  • VH_DLYSFX — list of file extensions for delays description entities (using $PATH syntax). The default file extension is dly.
  • VH_MAXERR — maximum number of errors allowed during simulation phase. If the number of errors occurred during simulation reaches VH_MAXERR, asimut stops the simulation at the end of processing the current pattern. Patterns following the current pattern remain unprocessed and are reproduced in the result file. The default value of VH_MAXERR is 10.

okay now the three files, let's talk about them properly 💅

root_file is the name of the description.

by default asimut looks for a structural description. it uses the MBK_IN_LO environment variables to identify both the format and the extension of structural description files. to load structural VHDL files, MBK_IN_LO must be set to vst. no cap.

to load a pure behavioural description, the -b option must be specified. in such a case asimut loads a data flow VHDL description file. the VH_BEHSFX environment variable gives the extensions to be used.

pattern_file is the entity name of the pattern description. the file containing this entity must be named pattern_file.ext, where ext is one of the extension specified in VH_PATSFX.

result_file is the result file produced by asimut. the result file is a pattern description file with the extension specified by VH_PATSFX.

💅 OPTIONS 💅

here's the whole list, all of them, i'm not skipping a single one, periodt.

  • -b — consider the root_file description as a behavioural description
  • -backdelay [min, max, typ] delay_file — use file delay_file.ext for delays backannotation, where ext is one of the extension specified in VH_DLYSFX.
  • -bdd — use BDDs (Binary Decision Diagram) to represent expressions. Using this option makes the simulation be two times faster but increases memory requirement
  • -c — run only the compilation stage
  • -core core_file — at the first error encountered, dump the state of the circuit in both an ascii file (suffixed .cor) and a binary save file (suffixed .sav) which can be used as initialization file in a further session. If the -nores option is specified a pattern file is also produced.
  • -dbg[sbpldc] — call the debugger (developer usage)
  • -defaultdelay (-dd) — only null delays (no after clause in the VHDL file) are changed if backannotated delays or fixed delays are specified.
  • -fixeddelay value (-fd value) — all delays of the description are fixed to value.
  • -h — display this help file
  • -i value — initialize all signals of the description with value. Value can be 0 or 1
  • -i save_file — read a save file and use it to initialize the state of the description before processing the first pattern (the file name cannot be 1 nor 0)
  • -inspect instance_name — produce a pattern file corresponding to the interface of the instance identified by instance-name
  • -l n — print at most n characters for pattern labels. The default value for n is 15.
  • -nores — do not generate result file
  • -p n — load at most n patterns from input pattern file each time. Using this feature reduces memory allocation when a great number of patterns are to be simulated. In addition after the n patterns have been processed, the simulation result is printed in the result pattern file. The default value for n is 0 which makes the whole pattern file be loaded.
  • -t — trace signals when making BDDs (developer usage).
  • -transport — use transport delay model (default is inertial).
  • -zerodelay (-zd) — all the delays of the VHDL description are supposed to be null delays.

🌈 EXAMPLE 🌈

asimut -b -i init_add adder_32 adder_patterns res_add

this simulates a behavioural description held in the file named adder_32.vbe using the pattern file adder_patterns.pat. the simulation results is written into res_add.pat and the description is initialized with the values contained in init_add.sav. 🫶 chef's kiss, honestly.

😭 DIAGNOSTICS 😭

register initializations in the pattern file allows changing the value of a register into a known value. however, using this feature to initialize a register before executing the first pattern is not recommended. register values (defined by the initialization statement) may be overwritten, since the description has not a coherent state before the first pattern.

so like… you can, but don't come crying to me when your register gets clapped. the description literally isn't coherent yet. 💀

🦋 SEE ALSO 🦋

vhdl(5), pat(5), genpat(1), mbk(1)

go read these, they're the supporting cast and they ate. ⭐

🍓 BUG REPORT 🍓

This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools.

fr fr, send the feedback. they literally asked. 🙈

and that's the whole page bestie! this one came from the ASIM/LIP6 era, dated October 1, 1997, so yeah it's vintage — but vintage is just another word for iconic. 💜 ✨ 🎀

📦 where this page comes from