VERILATOR(1)
π VERILATOR π
ok so bestie, this is the manual page for Verilator, from the User Contributed Perl Documentation section β yes it lives in the Perl docs section, no we're not going to explain that, just roll with it π«Ά
β¨ NAME β¨
Verilator β lint, compile and simulate SystemVerilog code using C++/SystemC
likeβ¦ it lints it, it compiles it, it simulates it. the whole trinity. periodt π
π SYNOPSIS π
here's the vibe check on how you actually call it:
verilator --help
verilator --version
verilator --binary -j 0 [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --lint-only -Wall [source_files.v]...
ok notice how --binary, --cc and --sc all take [options] plus your [source_files.v]... plus optional C++ files that are .cpp/.c/.cc/.a/.o/.so β those are the "opt_c_files", like optional C files, not "optimal C files" (ngl i made that mistake too π). and yeah -j 0 is in the --binary line, iconic.
π DESCRIPTION π
ok so the "Verilator" package β that's the literal package name, quotes and all β converts all synthesizable designs, and many behavioral ones, from Verilog and SystemVerilog into a C++ or SystemC model. then, after you compile that model, you can execute it. slay π
but here's the thing that makes Verilator not like the other girls: Verilator is not a traditional simulator, but a compiler. that's the whole personality. it's giving compiler energy, not simulator energy. no cap π₯
for documentation, go look at <https://verilator.org/verilator_doc.html> β that's the link, that's where the docs live, go get 'em π¦
π ARGUMENT SUMMARY π
this is just a short summary of the arguments you can pass to the "verilator" executable β like a little appetizer, not the full meal. for the detailed descriptions of these arguments, the manpage points you at <https://verilator.org/guide/latest/exe_verilator.html>. so if you want the whole story, that's the link bestie π
the files you can hand it:
<file.v>β Verilog package, module, and top module filenames πΈ<file.c/cc/cpp>β optional C++ files to compile in β¨<file.a/o/so>β optional C++ files to link in π
more parts follow, so don't go anywhere β we're literally just getting started π
...and the language-vibe extension options keep going, bestie β¨:
+1364-1995ext+<ext>β parse files with extension<ext>as Verilog 1995, periodt π+1364-2001ext+<ext>β same deal, but Verilog 2001+1364-2005ext+<ext>β and Verilog 2005+1800-2005ext+<ext>β switch that extension to SystemVerilog 2005 era+1800-2009ext+<ext>β SystemVerilog 2009, she's evolved+1800-2012ext+<ext>β SystemVerilog 2012, still iconic+1800-2017ext+<ext>β SystemVerilog 2017, lowkey the standard one+1800-2023ext+<ext>β SystemVerilog 2023, freshest of the fresh π¦
Now the actual flags, alphabetically-ish, no skips:
--no-aslrβ disable address space layout randomization. ASLR? not today π--no-assertβ turn off all the assertions. every single one.--no-assert-caseβ turn off just theunique/unique0/priority-case assertions, if you only want those gone--assert-unroll-limit <iter>β the max number of SVA assertion repetitions before it gives up and errors out--autoflushβ flush streams after all the$displays run πΏ--bbox-sysβ blackbox any$systemcalls it doesn't recognize--bbox-unsupβ blackbox language features it doesn't support, so it doesn't β¨panicβ¨--binaryβ build the model as a binary--buildβ build the model executable/library after Verilation--build-dep-bin <filename>β override which Verilator binary the build dependency uses--build-jobs <jobs>β how much parallelism to throw at--buildπ―--ccβ create C++ output-CFLAGS <flags>β C++ compiler arguments that go in the makefile--compiler <compiler-name>β tune everything for the C++ compiler you named--compiler-includeβ stick an extra header into the precompiled one--constraint-array-limit <size>β max array size for constraint array reduction--converge-limit <loops>β tune how long convergence is allowed to settle, like letting the tea steep π΅--coverageβ turn on all the coverage. the whole buffet π--coverage-branchβ branch coverage--coverage-exprβ expression coverage--coverage-expr-max <value>β max permutations it'll allow for a single expression--coverage-fsmβ FSM state/arc coverage--coverage-fsm-expand <mode>β pick the mode for fsm arc expansion--coverage-fsm-max-arcs <value>β cap on how many transitions an expanded FSM can have--coverage-lineβ line coverage--coverage-max-bins <value>β max bins for an integral coverpointbinsdeclaration--coverage-max-real-bins <value>β same, but for a real coverpointbinsdeclaration--coverage-max-width <width>β max array depth for coverage--coverage-merge-instancesβ default covergroups to merge their instances π«--coverage-per-instanceβ per-instance coverage counters instead--coverage-toggleβ toggle coverage--coverage-underscoreβ enable coverage of_signals--coverage-userβ enable SVL user coverage-D<var>[=<value>]β set a preprocessor define--debugβ debugging mode ON--debug-checkβ debugging assertions ON--no-debug-leakβ don't leak memory in--debugmode (yes, the leak is normally, like, a feature π)--debugi <level>β debugging at a specific level--debugi-<srcfile> <level>β debugging for one specific source file at a level--no-decorationβ no comments, lower spacing level--decorations <level>β set the output comment and spacing level--default-language <lang>β which language to parse by default+define+<var>=<value>β set a preprocessor define, plus-sign style--diagnostics-sarifβ turn on SARIF diagnostics output--diagnostics-sarif-output <filename>β pick the SARIF diagnostics output file--dpi-hdr-onlyβ only cough up the DPI header file, nothing else--dump-<srcfile>β dump everything from that source file--dump-ast-patternsβ dump Ast pattern statistics--dump-definesβ show preprocessor defines when you use-E--dump-dfgβ dump DfgGraphs to.dotfiles--dump-dfg-patternsβ dump Dfg pattern statistics--dump-graphβ dump V3Graphs to.dotfiles--dump-inputsβ dump the preprocessed input files--dump-treeβ dump Ast.treefiles--dump-tree-addridsβ use short identifiers instead of addresses--dump-tree-dotβ dump Ast.tree.dotdebug files--dump-tree-jsonβ dump Ast.tree.jsonfiles and a.tree.meta.jsonfile--dumpi-<srcfile> <level>β dump everything from that source file, at a level--dumpi-dfg <level>β dump DfgGraphs to.dotfiles, at a level--dumpi-graph <level>β dump V3Graphs to.dotfiles, at a level--dumpi-tree <level>β dump Ast.treefiles, at a level--dumpi-tree-json <level>β dump Ast.tree.jsonfiles, at a level-Eβ preprocess only, do NOT compile. she's just reading π--emit-accessorsβ emit getter and setter methods for the model's top class--error-limit <value>β abort after this many errors--exeβ link it up to create an executable--expand-limit <value>β set the expand optimization limit-F <file>β parse arguments from a file, relatively (iykyk)-f <file>β parse arguments from a file, non-relatively-FI <file>β force include a file--flattenβ force-inline every module, task and function. no nesting, only vibes π«Ά--fourstateβ turn on fourstate logic--no-fourstateβ turn it back off--func-recursion-depth <value>β max recursion depth for constant functions--future0 <option>β ignore an option for compatibility--future1 <option>β ignore an option with an argument for compatibility-fno-<optimization>β disable a specific internal optimization stage-G<name>=<value>β overwrite a top-level parameter--gate-stmts <value>β tune gate optimizer depth--gdbβ run Verilator under GDB, interactively π--gdbbtβ run Verilator under GDB just to get a backtrace--generate-keyβ create a random key for--protect-key--get-supported <feature>β ask whether a feature is supported--getenv <var>β get an environment variable, with defaults--helpβ show this help. hi, that's this π--hierarchicalβ turn on hierarchical Verilation--hierarchical-block <block>β internal use only for--hierarchical--hierarchical-child <block>β internal use only for--hierarchical--hierarchical-params-file <name>β internal option that specifies the parameters file for hier blocks--hierarchical-threads <threads>β number of threads for hierarchical scheduling-I<dir>β a directory to search for includes--if-depth <value>β tune theIFDEPTHwarning+incdir+<dir>β a directory to search for includes, plus-sign style--inline-cfuncs <value>β inline CFuncs with<=valuenodes (0=off)--inline-cfuncs-product <value>β inline CFuncs ifsize*calls <= value--inline-mult <value>β tune module inlining--instr-count-dpi <value>β assumed dynamic instruction count of DPI imports-j <jobs>β parallelism for--build-jobs/--verilate-jobs--no-json-edit-numsβ don't dumpeditNumin.tree.jsonfiles--no-json-idsβ don't use short identifiers instead of addresses/paths in.tree.json--json-onlyβ create JSON parser output only (.tree.jsonand.meta.json)--json-only-meta-output <filename>β set the.tree.meta.jsonoutput filename--json-only-output <filename>β set the.tree.jsonoutput filename--l2-name <value>β the Verilog scope name of the top module--language <lang>β the default language standard to parse-LDFLAGS <flags>β linker pre-object arguments for the makefile-libmapβ specify the library mapping file--lib-create <name>β create a DPI library+libext+<ext>+[ext]...β extensions for finding modules+librescanβ ignored for compatibility (she's just here, being polite)--lint-onlyβ lint it, but make no output at all--localize-max-size <value>β tune the localize optimization variable size--mainβ generate a C++main()file--main-top-nameβ specify the top name passed to the Verilated model in the generated C++main--make <build-tool>β generate scripts for whichever build tool you name-MAKEFLAGS <flags>β arguments to pass to make during--build--max-num-width <value>β maximum number width (default:64K)--Mdir <directory>β name of the output object directory--MMDβ create.ddependency files--mod-prefix <topname>β name to prepend to the lower classes--MPβ create phony dependency targets+notimingchecksβ ignored-o <executable>β name of the final executable-O0β disable optimizations-O1β the default optimizations-O2β stronger optimizations-O3β high-performance optimizations π₯-O<optimization-letter>β pick your own selectable optimizations, choose-your-own-adventure style--output-groups <numfiles>β group.cppfiles into bigger ones--output-groups-size <bytes>β limit how big those grouped.cppfiles can get--output-split <statements>β split.cppfiles into pieces--output-split-cfuncs <statements>β split model functions--output-split-ctrace <statements>β split tracing functions-Pβ disable line numbers and blanks when using-E--pins-bv <bits>β specify types for top-level ports--pins-inout-enablesβ specify that__enand__outsignals get created for inouts--pins-sc-biguintβ specify types for top-level ports--pins-sc-uintβ specify types for top-level ports--pins-sc-uint-boolβ specify types for top-level ports--pins-uint8β specify types for top-level ports--no-pins64β don't useuint64_t's for 33-64 bit sigs--pipe-filter <command>β filter all input through a script π--prefix <topname>β name of the top-level class--preproc-commentsβ include preprocessor comments in the output when using-E--preproc-definesβ include preprocessor defines in the output when using-E--preproc-resolveβ include all found modules in the output when using-E--preproc-token-limitβ maximum tokens on a line the preprocessor will allow--privateβ debugging; see docs π΅οΈ--prof-cβ compile the C++ code with profiling--prof-cfuncsβ name functions for profiling--prof-execβ generates an execution profile for the gantt chart π--prof-pgoβ generates profiling data for PGO π₯--protect-idsβ hashes identifier names for obscurity π--protect-key <key>β the key used for symbol protection π--protect-lib <name>β makes a DPI protected library π--publicβ marks signals as public; see docs π--public-depth <level>β marks public out to the specified module depth π«§--public-flat-rwβ marks all variables, etc., aspublic_flat_rw--public-ignoreβ ignores all public comment markings π--public-paramsβ marks all parameters aspublic_flat-pvalue+<name>=<value>β overwrites a toplevel parameter βοΈ--quietβ minimizes additional printing π€«--quiet-buildβ doesn't print build progress--quiet-exitβ doesn't print the command on failure--quiet-statsβ doesn't print statistics--relative-includesβ resolves includes relative to the current file π--reloop-limit <value>β minimum iterations for forming loops π--replication-limit <value>β replication concatenation limit (default:8k) π--report-unoptflatβ extra diagnostics forUNOPTFLATπ©Ί--rrβ runs Verilator and records withrrβΊοΈ--runtime-debugβ enables model runtime debugging π--savableβ enables model save-restore πΎ--scβ creates SystemC output--sched-zero-delayβ specifies#0delay support β±οΈ--no-skip-identicalβ disables skipping identical output--statsβ creates a statistics file π--stats-varsβ provides statistics on variables--no-stdβ prevents loading standard files π«--no-std-packageβ prevents parsing the standard package--no-std-waiverβ prevents parsing standard lint waivers--no-stop-failβ does not call$stopwhen an assertion fails-svβ enables SystemVerilog parsing β¨+systemverilogext+<ext>β synonym for+1800-2023ext+<ext>--threads <threads>β enables multithreading π§΅--threads-dpi <mode>β enables multithreaded DPI--threads-max-mtasks <mtasks>β tunes the maximum mtask partitioning--timescale <timescale>β sets the default timescale β°--timescale-override <timescale>β overrides all timescales π€--timingβ enables timing support--no-timingβ disables timing support--top <topname>β alias of--top-moduleπ―--top-module <topname>β name of the top-level input module π--traceβ enables VCD waveform creation π--trace-coverageβ enables tracing of coverage--trace-depth <levels>β depth of tracing--trace-fstβ enables FST waveform creation--trace-max-array <depth>β maximum array depth for tracing--trace-max-width <width>β maximum bit width for tracing--trace-paramsβ enables tracing of parameters--trace-saifβ enables SAIF file creation--trace-structsβ enables tracing structure names ποΈ--no-trace-topβ does not emit traces for signals in the top module generated by verilator--trace-underscoreβ enables tracing of_signals (the underscore ones π)--trace-vcdβ enables VCD waveform creation-U<var>β undefines a preprocessor define--no-unlimited-stackβ doesn't disable the stack size limit π--unroll-count <loops>β tunes maximum loop iterations--unroll-limit <loops>β maximum loop iterations before assuming an infinite loop π--unroll-stmts <stmts>β tunes maximum loop body size--unused-regexp <regexp>β tunesUNUSEDlint signals-Vβ verbose version and config βΉοΈ-v <filename>β Verilog library--valgrindβ runs Verilator under valgrind π΅οΈ--no-verilateβ skips Verilation and just compiles previously Verilated code βοΈ--verilate-jobsβ job threads for the Verilation stage+verilog1995ext+<ext>β synonym for+1364-1995ext+<ext>+verilog2001ext+<ext>β synonym for+1364-2001ext+<ext>--versionβ shows program version and exits π--vpiβ enables VPI compiles π--waiver-multilineβ creates a multiline--matchfor waivers--waiver-output <filename>β creates a waiver file based on linter warnings π-Wallβ enables all style warnings π¨-Werror-<message>β converts warnings to errors π±-Wfuture-<message>β disables unknown message warnings-Wno-<message>β disables a warning-Wno-contextβ disables source context on warnings-Wno-fatalβ disables fatal exit on warnings-Wno-lintβ disables all lint warnings-Wno-styleβ disables all style warnings-work <libname>β sets the config library for following files ποΈ-Wpedanticβ warns on compliance-test issues π§-Wwarn-<message>β enables the specified warning message-Wwarn-lintβ enables the lint warning message-Wwarn-styleβ enables the style warning message--x-assign <mode>β assigns non-initial X's to this value β--x-initial <mode>β assigns initial X's to this value--x-initial-edgeβ enables initial X->0 and X->1 edge triggers β‘-y <dir>β directory to search for modules π
π the runtime args (the ones your simulation eats) π
okay so this is a short summary of the simulation runtime arguments, i.e. the args for the final Verilated simulation runtime models. for the detailed description of these arguments, go look at <https://verilator.org/guide/latest/exe_verilator.html> β that's where the full tea is β
+verilator+assert+lockβ locks assertion status changes at startup π+verilator+coverage+file+<filename>β sets the coverage output filename+verilator+debugβ enables debugging π+verilator+debugi+<value>β enables debugging at a level+verilator+error+limit+<value>β sets the error limit+verilator+helpβ shows help π+verilator+log+file+<filename>β logs stdout and stderr output to filename+verilator+noassertβ disables assert checking+verilator+prof+exec+file+<filename>β sets the execution profile filename+verilator+prof+exec+start+<value>β sets the execution profile starting point+verilator+prof+exec+window+<value>β sets the execution profile duration+verilator+prof+vlt+file+<filename>β sets the PGO profile filename+verilator+quietβ minimizes additional printing π€«+verilator+rand+reset+<value>β sets the random reset technique π²+verilator+rand+sampler+<name>β chooses what samplesrandomize()results+verilator+seed+<value>β sets the random seed π±+verilator+solver+file+<filename>β sets the random solver log filename+verilator+Vβ shows verbose version and config+verilator+versionβ shows version and exits π+verilator+vpi+<library>[:<bootstrap>]β loads the VPI shared library π+verilator+wno+unsatconstr+<value>β disables constraint warnings
π DISTRIBUTION π
the latest version lives at <https://verilator.org> β go get it bestie, it's free π
Copyright 2003-2026 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. π
All Verilog and C++/SystemC code quoted within this documentation file are released as Creative Commons Public Domain (CC0). Many example files and test files are likewise released under CC0 into effectively the Public Domain as described in the files themselves. π«Ά
π SEE ALSO π
verilator_coverageverilator_ganttverilator_profcfuncmake"verilator --help"β which is the source for this document π- <https://verilator.org/verilator_doc.html> β for detailed documentation β¨
and that's the whole page, bestie!! you made it to the end, iconic behavior honestly π go verilate something beautiful π¦
this page isperl v5.44.0, dated2026-11-01, and it'sVERILATOR(1)β like a little time capsule in manpage form π ngl that date is giving future main character energy fr fr πΈ
π¦ where this page comes from
- arch rolling: verilator 5.054-1 Β· LGPL-3.0-only AND Artistic-2.0
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms