LIKWID-FEATURES(1)

πŸ’… likwid-features β€” the manual page, but make it make sense

okay bestie, gather round, because this one is all about likwid-features, a lil command-line app from the LIKWID fam that lives in the General Commands Manual section. she's Intel-only, she's nosy about your CPU, and she's lowkey on her way out the door (more on that in a sec) 🫢


✨ SYNOPSIS ✨

likwid-features [-vhal] [-c cpus] [-e taglist] [-d taglist]

🌸 DESCRIPTION 🌸

so likwid-features is a command line application that prints out the flags sitting inside the model specific register (MSR) called MSR_IA32_MISC_ENABLE on Intel x86 processors. that's the whole vibe. she reads the register, she shows you what's in it. πŸ’–

on Core2 and later processors, she can also toggle the hardware prefetch flags. yes, actually toggle them. main character energy fr.

okay important: this does NOT work on AMD processors. not a single feature. don't come for her, she was built for Intel and she's sticking to it πŸ’€

for the documentation on what flags are supported on which processor, go check the Intel Software Developer's Manual Volume 3B, Table B.2 and also this link: https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors

the MSR are set individually for every hardware thread. so like, one at a time per thread, no short cuts bestie.

🚨 heads up: this tool will be deprecated in 5.4. enjoy her while she's here 😭

and these are the following hardware prefetchers you can toggle, no cap:

  • HW_PREFETCHER: Hardware prefetcher.
  • CL_PREFETCHER: Adjacent cache line prefetcher.
  • DCU_PREFETCHER: when the DCU prefetcher detects multiple loads from the same line done within a time limit, the DCU prefetcher assumes the next line will be required. the next line is prefetched in to the L1 data cache from memory or L2. she's reading the room and guessing ahead ✨
  • IP_PREFETCHER: the IP prefetcher is an L1 data cache prefetcher. the IP prefetcher looks for sequential load history to determine whether to prefetch the next expected data into the L1 cache from memory or L2. pattern recognition queen πŸ‘‘

✨ OPTIONS ✨

  • -v β€” prints version information to standard output, then exits. short and sweet, she tells you who she is then dips πŸ’…
  • -h β€” prints a help message to standard output, then exits. your friendly lil cheat sheet.
  • -a β€” List out the names of all detected features. all of them, named, on display πŸŽ€
  • -l β€” Print the state of all features for the given CPUs. what's on, what's off, for the CPUs you picked.
  • -c cpus β€” set on which hardware threads the MSR should be read and written. Syntax according to likwid-pin(1). so if you already know how to write CPU lists for likwid-pin(1), you already know how to write them here πŸ¦‹
  • -d HW_PREFETCHER | CL_PREFETCHER | DCU_PREFETCHER | IP_PREFETCHER β€” specify which prefetcher should be disabled. Argument can be a comma-separated list. so yeah, you can line up multiple ones and switch 'em all off in one go πŸ™ˆ
  • -e HW_PREFETCHER | CL_PREFETCHER | DCU_PREFETCHER | IP_PREFETCHER β€” specify which prefetcher should be enabled. Argument can be a comma-separated list. same energy, opposite direction, turn the babies back on 🌈

πŸ‘‘ AUTHOR πŸ‘‘

Written by Thomas Gruber <thomas.roehl@googlemail.com>. give her a lil moment of appreciation, she built this 🫢


πŸ’€ BUGS πŸ’€

Report Bugs on <https://github.com/RRZE-HPC/likwidissues>. that's the link, that's where the bugs go, don't @ her anywhere else.


🌟 SEE ALSO 🌟

likwid-pin(1), likwid-topology(1), likwid-perfctr(1). the rest of the squad, go say hi 🧚


aaand that's the page bestie πŸ’– she's from likwid-5, dated 23.12.2025, and she came to you courtesy of the LIKWID-FEATURES(1) manual. now go check your prefetchers, iykyk πŸŽ€βœ¨

πŸ“¦ where this page comes from