DRUC(1)

📦 version 5.1.1-unstable-2025-02, in nixos 26.05, nixpkgs unstable

🌸 DRUC(1) — the design rule checker that eats 💅

okay bestie so you've opened the manual page for druc, short for Design Rule Checker, and honestly? slay. this one's the ALLIANCE user command you've been looking for. let's get into it ✨

✨ SYNOPSIS ✨

druc input_name [ -v ] [ -h ]

that's it. that's the whole incantation. input_name is your cell, and then you get to sprinkle optional flags on top like little fairy dust 🧚

🌈 ORIGIN 🌈

okay so this software is not just some random thing off the internet — it belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France. very "study abroad semester in Paris but make it EDA" energy 🥐👑

the links, in case you want to send them a little thank-you note:

🦋 DESCRIPTION 🦋

DRuC is a general parametrized VLSI design rule checker. like, a general one. parametrized and everything. it checks your design rules, which is literally the whole point, and it does it for VLSI layouts 🫶

real talk though: this tool replaces the VERSATIL tool, which — and I'm gonna be gentle about this — is not anymore supported. so if you were clinging to VERSATIL, bestie, it's giving retired. move on. DRuC is the main character now 👑

🎀 the layout rules 🎀

this manual presents the layout rules for the ALLIANCE symbolic layout approach 📐 and the important thing is where those rules live: they're described in a technology file, and that technology file is defined by the environment variable RDS_TECHNO_NAME (see below). so yeah — that env var is doing a lot of heavy lifting. set it. love it. respect it.

🍓 where your files have to be 🍓

  • the root cell must be in the current directory
  • all the instantiated cells must be in the current directory too
  • with one exception: the instantiated libraries cells — those get a pass 🙈

so like, current directory is the vibe. don't go wandering 🚶‍♀️

💀 the default mode (read this part) 💀

the default mode of DRuC is (currently) full flat. and what that means is it first flattens all the hierarchy in order to obtain a flat, rectangle level description.

literally all of it. the whole hierarchy. gone. flattened. into rectangles. no cap 😭 so if you were expecting hierarchy to be respected, it's not — not by default anyway, and definitely not "currently". noted in the manual with a casual "(currently)" like that isn't going to change your whole life 💀

💅 OPTIONS 💅

  • -v — verbosity: ON. every single step of the DRC gets output on the standard output, so you can watch the whole thing happen in real time like a little reality show 🔥 obsessed.
  • -h — hierarchical design rule checking. fair warning: this one generates lots of files locally, and those files exist to be used by future invocation of druc. so it's not a one-and-done situation, it's a whole ongoing relationship 💖 and as for whether it actually works and how? the manual itself says, and I quote, "Don't ask me if and how this works, but since you also fetched the sources, ..." — so like. the docs have decided not to answer that one. deeply iconic of them. if you want the tea you're gonna have to read the source 🫖👀
ngl the -h flag leaving us on a cliffhanger with a literal trailing ... is the most mysterious thing in this entire page and I respect it 🎀

🎀 DESIGN RULES DESCRIPTION 🎀

0: LAYER NAME

Bestie, before we get into the rules, here's the cast of characters — this little bit spells out exactly which layer name means what in everything that follows 💅

  • NWELL — N well
  • NTIE — N well polarisation
  • PTIE — P substrat polarisation
  • NDIF — N diffusion
  • PDIF — P diffusion
  • GATE — transistor gate
  • POLY — polysilicon wire
  • ALU1 — first level of metal
  • ALU2 — second level of metal
  • CONT — contact between ALU1 and POLY or DIFF
  • VIA — contact between ALU1 and ALU2

I: LAYER WIDTH

Okay so this whole category is about how thin a layer is allowed to get 🌸 — the width limits of a layer — plus the conditions for equipotentiality between two segments that overlap or abut. Not me being obsessed with the exact numbers, but like, the exact numbers matter.

  • rule 1 — the minimum width for a segment of NWELL is 4. corresponding error codes are: 100 101
  • rule 2 — the minimum width for a segment of NTIE is 2. corresponding error code is: 119
  • rule 3 — the minimum width for a segment of PTIE is 2. corresponding error codes are: 122 123
  • rule 4 — the minimum width for a segment of NDIF is 2. corresponding error codes are: 140 141
  • rule 5 — the minimum width for a segment of PDIF is 2. corresponding error codes are: 165 166
  • rule 6 — the minimum width for a segment of GATE is 1. corresponding error codes are: 234 235
  • rule 7 — the minimum width for a segment of POLY is 1. corresponding error codes are: 234 235
  • rule 8 — the minimum width for a segment of ALU1 is 1. corresponding error codes are: 238 239
  • rule 9 — the minimum width for a segment of ALU2 is 2. corresponding error codes are: 242 243
  • rule 10 — the width of a CONT must be equal to 1. corresponding error codes are: 246 247
  • rule 11 — the width of a VIA must be equal to 1. corresponding error codes are: 261 262

II: FORBIDDEN OVERLAP

This class of rules is the "do NOT let these two layers touch" list 🙈 — it specifies the forbidden overlaps between two layers. And when we say forbidden, we mean the distance between them must be strictly positive, no cap, not even a little kiss.

  • rule 12 — contact between PTIE and NWELL is forbidden. corresponding error codes are: 126 127 128 129 130 131
  • rule 13 — contact between PTIE and NTIE is forbidden. corresponding error codes are: 133 134 135 136 137 138
  • rule 14 — contact between NDIF and NWELL is forbidden. corresponding error codes are: 144 145 146 147 148 149
  • rule 15 — contact between NDIF and NTIE is forbidden. corresponding error codes are: 151 152 153 154 155 156
  • rule 16 — contact between NDIF and PTIE is forbidden. corresponding error codes are: 158 159 160 161 162 163
  • rule 17 — contact between PDIF and NTIE is forbidden. corresponding error codes are: 169 170 171 172 173 174
  • rule 18 — contact between PDIF and PTIE is forbidden. corresponding error codes are: 176 177 178 179 180 181
  • rule 19 — contact between PDIF and NDIF is forbidden. corresponding error codes are: 183 184 185 186 187 188
  • rule 20 — contact between GATE and NTIE is forbidden. corresponding error codes are: 191 192 193 194 195 196
  • rule 21 — contact between GATE and PTIE is forbidden. corresponding error codes are: 198 199 200 201 202 203
  • rule 22 — contact between POLY and NTIE is forbidden. corresponding error codes are: 207 208 209 210 211 212
  • rule 23 — contact between POLY and PTIE is forbidden. corresponding error codes are: 214 215 216 217 218 219
  • rule 24 — contact between POLY and NDIF is forbidden. corresponding error codes are: 221 222 223 224 225 226
  • rule 25 — contact between POLY and PDIF is forbidden. corresponding error codes are: 228 229 230 231 232 233
  • rule 26 — contact between CONT and GATE or POLY is forbidden. corresponding error codes are: 249 250 251 252 253
  • rule 27 — contact between VIA and GATE is forbidden. corresponding error codes are: 264 265 266 267 268 269
  • rule 28 — contact between VIA and POLY is forbidden. corresponding error codes are: 271 272 273 274 275 276
  • rule 29 — contact between VIA and CONT is forbidden. corresponding error codes are: 278 279 280 281 282 283
  • rule 30 — contact between NTIE and NWELL is forbidden. corresponding error code is: 109
  • rule 31 — contact between PDIF and NWELL is forbidden. corresponding error code is: 117

III: LAYER NOTCH

Notches, bestie — the little inner corners 🦋. This class of rules deals with the notch limits of a layer.

  • rule 32 — the minimum notch for a segment of NWELL is 4. corresponding error code is: 102
  • rule 33 — the minimum notch for a segment of NTIE is 2. corresponding error code is: 120
  • rule 34 — the minimum notch for a segment of PTIE is 2. corresponding error code is: 124
  • rule 35 — the minimum notch for a segment of NDIF is 2. corresponding error code is: 142
  • rule 36 — the minimum notch for a segment of PDIF is 2. corresponding error code is: 167
  • rule 37 — the minimum notch for a segment of POLY is 1. corresponding error code is: 236
  • rule 38 — the minimum notch for a segment of ALU1 is 2.5. corresponding error code is: 240
  • rule 39 — the minimum notch for a segment of ALU2 is 2. corresponding error code is: 244

IV: MINIMUM SPACING

Distance makes the heart grow fonder 💖 — this class of rules specifies the minimum edge-to-edge distance allowed between two layers.

heads up: the rule numbers in this list do a little hop-skip — 41 and 50 just aren't here in the original, that's genuinely how it's written, not me dropping anything 🫶
  • rule 40 — the minimum distance between NWELL and NWELL is 12. corresponding error code is: 118
  • rule 42 — the minimum distance between NTIE and NTIE is 3. corresponding error code is: 121
  • rule 43 — the minimum distance between PTIE and NWELL is 7.5. corresponding error code is: 125
  • rule 44 — the minimum distance between PTIE and NTIE is 8. corresponding error code is: 132
  • rule 45 — the minimum distance between PTIE and PTIE is 3. corresponding error code is: 139
  • rule 46 — the minimum distance between NDIF and NWELL is 7.5. corresponding error code is: 143
  • rule 47 — the minimum distance between NDIF and NTIE is 8. corresponding error code is: 150
  • rule 48 — the minimum distance between NDIF and PTIE is 3. corresponding error code is: 157
  • rule 49 — the minimum distance between NDIF and NDIF is 3. corresponding error code is: 164
  • rule 51 — the minimum distance between PDIF and NTIE is 3. corresponding error code is: 168
  • rule 52 — the minimum distance between PDIF and PTIE is 8. corresponding error code is: 175
  • rule 53 — the minimum distance between PDIF and NDIF is 8. corresponding error code is: 182
  • rule 54 — the minimum distance between PDIF and PDIF is 3. corresponding error code is: 189
  • rule 55 — the minimum distance between GATE and NTIE is 1. corresponding error code is: 190
  • rule 56 — the minimum distance between GATE and PTIE is 1. corresponding error code is: 197
  • rule 57 — the minimum distance between GATE and NDIF is 1. corresponding error code is: 204
  • rule 58 — the minimum distance between GATE and PDIF is 1. corresponding error code is: 205
  • rule 59 — the minimum distance between GATE and GATE is 2. corresponding error code is: 237
  • rule 60 — the minimum distance between POLY and NTIE is 1. corresponding error code is: 206
  • rule 61 — the minimum distance between POLY and PTIE is 1. corresponding error code is: 213
  • rule 62 — the minimum distance between POLY and NDIF is 1. corresponding error code is: 220
  • rule 63 — the minimum distance between POLY and PDIF is 1. corresponding error code is: 227
  • rule 64 — the minimum distance between POLY and GATE is 2. corresponding error code is: 237
  • rule 65 — the minimum distance between POLY and POLY is 2. corresponding error code is: 237
  • rule 66 — the minimum distance between ALU1 and ALU1 is 2.5. corresponding error code is: 241
  • rule 67 — the minimum distance between ALU2 and ALU2 is 2. corresponding error code is: 245
  • rule 68 — the minimum distance between CONT and CONT is 3. corresponding error code is: 254
  • rule 69 — the minimum distance between VIA and GATE is 2. corresponding error code is: 263
  • rule 70 — the minimum distance between VIA and POLY is 2. corresponding error code is: 270
  • rule 71 — the minimum distance between VIA and CONT is 2. corresponding error code is: 277
  • rule 72 — the minimum distance between VIA and VIA is 3. corresponding error code is: 284
  • rule 73 — the minimum distance between CONT and GATE or POLY is 1.5. corresponding error code is: 248

V: TOTAL INCLUSION

Last class, bestie — this one is all about one layer being fully included inside another one, like a lil nesting moment 🧚

  • rule 74 — NTIE must be included in NWELL with a minimun margin of 0.5. corresponding error code is: 103
  • rule 75 — PDIF must be included in NWELL with a minimun margin of 0.5. corresponding error code is: 110

🌈 FILES 🌈

If design errors are found, DRuC produces the list of them in two files, and honestly that's iconic of it:

  • <root_name.drc>: This ascii file contains the list of DRC violations.
  • <root_name.iii>: This gds ro cif file contains only rectangles detected in violation. ( suffix iii is defined with the environment )

RDS_OUT_PH is default setted to gds.

✨ ENVIRONMENT VARIABLES ✨

DRuC uses several environment variables, so keep these besties in mind:

  • MBK_IN_PH — defines the layout input format.
  • RDS_OUT_PH — defines the layout output format.
  • RDS_TECHNO_NAME — defines the technology file.
  • MBK_CATA_LIB — defines the catalog directory.

See the corresponding manual pages for further information 👑

🍓 EXAMPLE 🍓

druc register

💀 BUG REPORT 💀

This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools 🫶

and that's the whole page, bestie — no crumbs left 💅 the footer energy is all ASIM/LIP6, and the page is dated October 1, 1997, living as DRUC(1). go off, run that DRC, and remember: strictly positive distances only 😭✨

📦 where this page comes from