COUGAR(1)

πŸ“¦ version 5.1.1-unstable-2025-02, in nixos 26.05, nixpkgs unstable

πŸ’… COUGAR(1) β€” the Alliance user commands era ✨

okay so this is the cougar page from the ALLIANCE USER COMMANDS manual section and bestie, we're gonna get through it together 🫢


✨ NAME ✨

cougar β€” hierarchical netlist extractor πŸ’– (yes, that's literally the whole job, and she ate)


πŸ¦‹ SYNOPSIS πŸ¦‹

cougar [ -v ] [ -c ] [ -f ] [ -t ] [ -ar ] [ -ac ] input_name [
output_name ]

periodt. that's the shape of it πŸ’…


🌸 ORIGIN 🌸

so this software belongs to the ALLIANCE CAD SYSTEM, developed by the ASIM team at the LIP6 laboratory of UniversitΓ© Pierre et Marie CURIE, in Paris, France πŸ‡«πŸ‡·βœ¨ iconic lineage ngl


πŸ’œ DESCRIPTION πŸ’œ

okay story time: Lynx changed its name to Cougar during May 2002 because of a name conflict with that famous text-mode Web browser 😭 like she was out here getting confused with a browser, embarrassing, so she rebranded and honestly? main character energy.

Cougar is a hierarchical layout extractor. She builds a netlist of interconnections from a symbolic layout view. The input argument is the name of the symbolic layout cell to be extracted, using as input format the one selected by the MBK_IN_PH(1) environment variable. If output is present, the resulting netlist will be given this name. If no output is given, then input will also be the generated netlist name. The output format is specified by the MBK_OUT_LO(1) environment variable.

As most of the Alliance cad tools, cougar uses mbk(1) environment variables β€” specifically:

  • MBK_CATA_LIB(1)
  • MBK_WORK_LIB(1)
  • MBK_IN_PH(1)
  • MBK_OUT_LO(1)
  • RDS_TECHNO_NAME(1)

πŸŽ€ the capacitance tea πŸŽ€

Cougar computes capacitances attached to the signals if the -ac option is set. At the moment, the value of these capacitances is computed for a typical one micron technology, and cannot be changed by the user through a technology file πŸ™ˆ (that's just how it is bestie, no cap). The extracted netlist can be simulated for performance evaluation.

The typical capacitances are given below in 10e-18 farad / lamda^2 :

  • POLY β€” 100
  • ALU1 β€” 50
  • ALU2 β€” 25

πŸ”₯ OPTIONS πŸ”₯

first, the vibe check: Cougar checks the two basic ALLIANCE rules regarding connector names πŸ‘‘

  • If two physical connectors are connected to the same net, they must have the same name.
  • If two physical connectors have the same name, they must be internally connected to the same net.

As a result only one logical connector will appear in the netlist. A fatal error occurs if one of those two rules is violated ( even for power and ground connectors ) πŸ’€ like, even the power and ground connectors, she does NOT play.

When no options are specified, the current hierarchical level is extracted. The resulting netlist is the list of interconnections of the current layout hierarchy level.

Three options are available to change cougar behaviour (plus the resistance/capacitance girlypops further down, iykyk) :

  • -t β€” Notifies a transistor level extraction, the symbolic layout cell is flattened to transistor layout before extraction. 🧚
  • -f β€” The symbolic layout cell is flattened to the catalog level before extraction. Use "man catal" for detail on the catalog file. If the catalog is empty, or doesn't exist, the netlist is an interconnection of transistors; if it isn't, the netlist is an interconnection of gates or blocks whose names are defined in the catalog. 🌈
  • -v β€” Verbose mode on. Each step of the extraction is displayed on the standard output, along with some statistics. πŸ‘€
  • -c β€” Generates a core file representing the conflictuel net, when cougar detects two external connectors with different names on the same signal, or when it finds two external connectors having the same name but not internally connected to the same net, or when it cannot correctly extract an L shaped transistor. 🫠 (yes, it dumps core on purpose, she's dramatic)
  • -ac β€” Extract capacitance to ground on losig. ⚑
  • -ar β€” Extract interconnect resistance and capacitance to ground. Value of resistance foreach layer can be changed in the RDS file. πŸ”§

⭐ EXAMPLES ⭐

πŸ’– example one β€” verbose, one level

prompt> cougar -v amd2901

Gives a logical netlist of the chip amd2901, for one hierarchical level, using verbose mode. This would be typically used to verify the work of the ring(1) router, in conjunction with lvx on the specificated netlist and the extracted one. slay πŸ’…

πŸ¦‹ example two β€” catalog peek

prompt> cat $MBK_WORK_LIB/$MBK_CATAL_NAME
a2_y
a2p_y
 .
 .

(that's you looking at your catalog file, cutie ✨)

prompt> cougar -f amd2901

Gives a logical netlist of the chip amd2901, after a flatten operation stopping on the cells specified in the catalog ( the standard cell library in our case ). πŸŽ€

🌸 example three β€” transistor level

prompt> cougar -t amd2901

Gives a logical netlist of the amd2901 chip at the transistor level. This is useful with yagle(1), to retrieve logical equations from a layout. obsessed honestly πŸ’œ


🌈 SEE ALSO 🌈

al(5), MBK_CATA_LIB(1), MBK_WORK_LIB(1), MBK_CATAL_NAME(1), MBK_IN_PH(1), catal(5), RDS_TECHNO_NAME(1).

go read those too bestie, they're all connected 🫢


πŸ’€ BUG REPORT πŸ’€

This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools. πŸ™ fr fr, tell them what's broken, they're literally asking.


πŸ’Œ and that's the page!! brought to you by ASIM/LIP6, dated October 1, 1997, filed under COUGAR(1) β€” mwah, go extract something iconic πŸ‘‘βœ¨
πŸ“¦ where this page comes from