ABC(1)

✨ NAME ✨

Okay bestie, welcome to ABC(1) 🎀 This is a User Commands page, so it's all the stuff you actually type into your terminal 💻

abc is for sequential logic synthesis and formal verification 🔥

🌸 SYNOPSIS 🌸

abc [OPTIONS] FILE

💖 DESCRIPTION 💖

Okay so, ABC is a growing software system for synthesizing and verifying binary sequential logic circuits, the kind that show up in synchronous hardware designs 🧚 It's giving scalable logic optimization based on And-Inverter Graphs (AIGs), plus optimal-delay DAG-based technology mapping for look-up tables and standard cells, plus innovative algorithms for sequential synthesis and verification. Main character energy, no cap ✨

ABC gives you an experimental implementation of these algorithms AND a programming environment for building similar applications 🦋 Future development is going to focus on improving the algorithms and making most of the packages stand-alone. The vibe is that you'll be able to customize ABC for your needs like it's a toolbox instead of one complete tool. Iconic 💅

🎀 OPTIONS 🎀

• -c CMD — Runs the commands in CMD 🍓
• -q CMD — Runs the commands in CMD, but quietly 🤫
• -C CMD — Runs the commands in CMD, then keeps you in interactive mode 🫶
• -Q CMD — Runs the commands in CMD quietly, then keeps you in interactive mode 🌙
• -F SCRIPT — Runs the commands from the script file SCRIPT and echoes each command as it goes 📜
• -f SCRIPT — Runs the commands from the script file SCRIPT, no echo 🧾
• -h — Prints the command usage. Lowkey the first thing to try if you're confused 🙈
• -o FILE — Stores the result in FILE 💜
• -s — Does NOT read any initialization file 🚫
• -t TYPE — Sets the input type. It has to be one of blif_mv, blif_mvs, blif, or none. The default is blif_mv 🌈
• -T TYPE — Sets the output type. Same choices as -t: blif_mv, blif_mvs, blif, or none. The default is blif_mv 🦄
• -x — Same as -t none -T none. Both input and output get set to none, bestie 🙃
• -b — Runs in bridge mode 🌉

🧚 INTRODUCTION 🧚

Okay this part is the tea ☕ Data structures and algorithms at the heart of a software system decide what it can do with data and how good it is as a programming environment for building new apps. The team had tons of experience with SIS, VIS, and MVSIS, and it was super clear that none of them gave a flexible programming environment for recent innovations, like combining technology mapping with retiming. SIS is outdated and kinda inefficient when it comes to large circuits 💀 VIS was designed as a formal verification tool for multi-valued specifications, so it doesn't have enough flexibility for binary synthesis. MVSIS got used a LOT for new synthesis algorithms on both multi-valued and binary networks 🔥 But then they realized two things: (a) the basic data structures and algorithms of MVSIS could be way simpler and easier to use if they assumed binary networks, and (b) the new system should be built around a new data structure, AIGs (multi-level logic networks made of two-input ANDs and inverters), which promises better quality and runtime for synthesis and verification ✨

So they redeveloped the core packages of MVSIS into a new programming environment called ABC 🎀 The name says it all: the main goal is to keep data structures simple and flexible for a wide range of applications. The "philosophy of ABC" has a few basic premises. One is allowing a variety of functional representations, like BDDs and SOPs, to handle specialized tasks, while defaulting to AIGs for mainstream network manipulation 🌸 Representing logic with AIGs leads to a remarkable uniformity in computation and makes it easy to interface with CNF-based SAT solvers for handling Boolean reasoning problems. Another big premise is the synergy between synthesis and verification, using efficient SAT-based Boolean reasoning on the AIG for combinational and sequential equivalence checking 🫶

The goal of the ABC project is to provide a public-domain implementation of state-of-the-art combinational and sequential synthesis algorithms, AND create an open-source environment where those applications can be developed and compared 🌈 The current version can optimize, map, and retime industrial gate-level designs with 100K gates and 10K sequential elements, for optimal delay and heuristically minimized area, in about one minute of CPU time on a modern computer 🚀 Combinational synthesis, mapping, and verification are typically even faster ⭐

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And that's the whole page, bestie 💅 Source/version: ABC 0.67 (2{gitdate}) 🦋 Go forth and synthesize, you literal genius 💖🎀