xilinx_dpdma...et_dma_addrs(9)

🎀 xilinx_dpdma...et_dma_addrs(9) 🎀

okay bestie, welcome to the Kernel API Manual page for this little icon ✨ yes the header is truncated and it's giving "we ran out of room" energy, but the function inside is xilinx_dpdma_sw_desc_set_dma_addrs, and we're gonna get you comfy with it 💖

✨ NAME ✨

xilinx_dpdma_sw_desc_set_dma_addrs — Set DMA addresses in the descriptor. that's the whole vibe: descriptor, DMA addresses, set. slay 💅

🦋 SYNOPSIS 🦋

void xilinx_dpdma_sw_desc_set_dma_addrs (struct xilinx_dpdma_device
*xdev , struct xilinx_dpdma_sw_desc *sw_desc , struct
xilinx_dpdma_sw_desc *prev , dma_addr_t dma_addr[] , unsigned int
num_src_addr );

🌸 ARGUMENTS 🌸

• xdev — DPDMA device. the main-character device, obviously 🫶
• sw_desc — The software descriptor in which to set DMA addresses. this is where the DMA addresses are going, bestie 🎀
• prev — The previous descriptor. the one before, if you have one 👀
• dma_addr — array of dma addresses. literally an array of DMA addresses, no cap ✨
• num_src_addr — number of addresses in dma_addr. how many little address besties are in that array 🔢

💅 DESCRIPTION 💅

Set all the DMA addresses in the hardware descriptor corresponding to dev from dma_addr. so it's taking the DMA addresses from dma_addr and putting them into the hardware descriptor for dev — very demure, very mindful 🧚

If a previous descriptor is specified in prev, its next descriptor DMA address is set to the DMA address of sw_desc. yes, prev's next-descriptor DMA address gets linked up to sw_desc's DMA address, iykyk 🔥

prev may be identical to sw_desc for cyclic transfers. and that's valid — same descriptor in both spots, no drama, cyclic transfers said "let me do it" 💀💖

🌈 SEE ALSO 🌈

Kernel file ./drivers/dma/xilinx/xilinx_dpdma.c plus the whole bestie list:

• struct xilinx_dpdma_hw_desc(9)
• struct xilinx_dpdma_sw_desc(9)
• struct xilinx_dpdma_tx_desc(9)
• struct xilinx_dpdma_chan(9)
• struct xilinx_dpdma_device(9)
• xilinx_dpdma_chan_alloc_sw_desc(9)
• xilinx_dpdma_chan_free_sw_desc(9)
• xilinx_dpdma_chan_dump_tx_desc(9)
• xilinx_dpdma_chan_alloc_tx_desc(9)
• xilinx_dpdma_chan_free_tx_desc(9)
• xilinx_dpdma_chan_prep_cyclic(9)
• xilinx_dpdma_chan_prep_interleaved_dma(9)
• xilinx_dpdma_chan_enable(9)
• xilinx_dpdma_chan_disable(9)
• xilinx_dpdma_chan_pause(9)
• xilinx_dpdma_chan_unpause(9)
• xilinx_dpdma_chan_queue_transfer(9)
• xilinx_dpdma_chan_ostand(9)
• xilinx_dpdma_chan_notify_no_ostand(9)
• xilinx_dpdma_chan_wait_no_ostand(9)
• xilinx_dpdma_chan_poll_no_ostand(9)
• xilinx_dpdma_chan_stop(9)
• xilinx_dpdma_chan_done_irq(9)
• xilinx_dpdma_chan_vsync_irq(9)
• xilinx_dpdma_chan_err(9)
• xilinx_dpdma_chan_handle_err(9)
• xilinx_dpdma_alloc_chan_resources(9)
• xilinx_dpdma_free_chan_resources(9)
• xilinx_dpdma_terminate_all(9)
• xilinx_dpdma_synchronize(9)
• xilinx_dpdma_err(9)
• xilinx_dpdma_handle_err_irq(9)
• xilinx_dpdma_enable_irq(9)
• xilinx_dpdma_disable_irq(9)
• xilinx_dpdma_chan_err_task(9)

okay bestie, that's the whole cute little page 💖 the source/version line is from ./drivers/dma/xilinx, it's dated October 2026, and the header on the tin is xilinx_dpdma...et_dma_addrs(9). go set those DMA addresses, you absolute icon 🎀✨