UNION NPS_CORE_INT_ENA_W1S(9)

💖 union nps_core_int_ena_w1s(9) 💖

okay so this is a page straight out of the Kernel API Manual, and it's all about union nps_core_int_ena_w1s — no cap, that's the whole title. Buckle up bestie, it's a bitfield girlie 🎀

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✨ NAME ✨

union nps_core_int_ena_w1s — the NPS core interrupt enable set register, and yes she's that girl 💅

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🌸 SYNOPSIS 🌸

ok so here's the whole shape of her, literally copy-paste it exactly, do not touch a single character of this, i'm begging 🫶

union nps_core_int_ena_w1s {
    u64 value;
    struct {
  #if (defined(__BIG_ENDIAN_BITFIELD));
      u64 raz4 : 55;
      u64 host_nps_wr_err : 1;
      u64 npco_dma_malform : 1;
      u64 exec_wr_timeout : 1;
      u64 host_wr_timeout : 1;
      u64 host_wr_err : 1;
      u64 raz3 : 1;
      u64 raz2 : 1;
      u64 raz1 : 1;
      u64 raz0 : 1;
  #else;
      u64 raz0 : 1;
      u64 raz1 : 1;
      u64 raz2 : 1;
      u64 raz3 : 1;
      u64 host_wr_err : 1;
      u64 host_wr_timeout : 1;
      u64 exec_wr_timeout : 1;
      u64 npco_dma_malform : 1;
      u64 host_nps_wr_err : 1;
      u64 raz4 : 55;
  #endif;
    } s;
 };

the way she's a union with a u64 value on top and a whole struct called s underneath… main character energy fr 👑

and like — vibe check — notice the #if (defined(__BIG_ENDIAN_BITFIELD)); / #else; / #endif; sandwich. the bit order flips depending on endianness, so the little one-bit fields start at the bottom on little-endian and at the top on big-endian. raz0 through raz3 live in one corner, raz4 : 55 takes up the whole rest of the party, and the five real ones are:

• host_nps_wr_err — 1 bit
• npco_dma_malform — 1 bit
• exec_wr_timeout — 1 bit
• host_wr_timeout — 1 bit
• host_wr_err — 1 bit

that's it, that's the whole squad 😭 also pls keep all the semicolons after #if, #else and #endif — they're part of the bitfield macro magic, don't @ me, just don't remove them 🙈

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🦋 Members 🦋

so the original just drops the word Members and then… nothing. an empty section. iconic honestly, she said "you'll figure it out" 💀 but yeah — the members are the ones up in the struct s above: value, and the field stack raz0, raz1, raz2, raz3, host_wr_err, host_wr_timeout, exec_wr_timeout, npco_dma_malform, host_nps_wr_err, raz4. that's the whole list, no gatekeeping ✨

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🌈 SEE ALSO 🌈

the friend group (iykyk), and yes every single one of them is going in here because we don't leave the girls out 💜

• union ucd_core_eid_ucode_block_num(9)
• union aqm_grp_execmsk_lo(9)
• union aqm_grp_execmsk_hi(9)
• union aqmq_drbl(9)
• union aqmq_qsz(9)
• union aqmq_cmp_thr(9)
• union aqmq_cmp_cnt(9)
• union aqmq_en(9)
• union aqmq_activity_stat(9)
• union emu_fuse_map(9)
• union emu_se_enable(9)
• union emu_ae_enable(9)
• union emu_wd_int_ena_w1s(9)
• union emu_ge_int_ena_w1s(9)
• union nps_pkt_slc_ctl(9)
• union nps_pkt_slc_cnts(9)
• union nps_pkt_slc_int_levels(9)
• union nps_pkt_in_done_cnts(9)
• union nps_pkt_in_instr_ctl(9)
• union nps_pkt_in_instr_rsize(9)
• union nps_pkt_in_instr_baoff_dbell(9)
• union nps_core_gbl_vfcfg(9)
• union nps_core_int_active(9)
• union efl_core_int(9)
• union efl_core_int_ena_w1s(9)
• union efl_rnm_ctl_status(9)
• union bmi_ctl(9)
• union bmi_int_ena_w1s(9)
• union bmo_ctl2(9)
• union pom_int_ena_w1s(9)
• union lbc_inval_ctl(9)
• union lbc_int_ena_w1s(9)
• union lbc_int(9)
• union lbc_inval_status(9)
• union rst_boot(9)
• union fus_dat1(9)

also she lives in the kernel file ./drivers/crypto/cavium/nitrox/nitrox_csr.h — go say hi 🧚

lowkey pro tip from the page itself: this is a _w1s register, meaning write 1 to set. that's literally in the name bestie, it's giving "touch it and it's on" 🔥

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and that's the whole thing, go off 💖

🌸🎀🦋 sign-off time 🦋🎀🌸

this lil beauty comes from ./drivers/crypto/cavium/nitrox and she's dated October 2026 — so yeah, mark your calendar, she's from the future and she still slaps 👑✨ periodt.