UNION FUS_DAT1(9)

union fus_dat1(9) 🎀

Kernel API Manual — yes bestie, we're reading a manpage for a union today, and honestly? It ate. 💅

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✨ NAME ✨

union fus_dat1 — the Fuse Data 1 Register. that's it, that's the whole vibe. 🔥

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🌸 SYNOPSIS 🌸

union fus_dat1 {
    u64 value;
    struct {
  #if (defined(__BIG_ENDIAN_BITFIELD));
      u64 raz_57_63 : 7;
      u64 pll_mul : 3;
      u64 pll_half_dis : 1;
      u64 raz_43_52 : 10;
      u64 efus_lck : 3;
      u64 raz_26_39 : 14;
      u64 zip_info : 5;
      u64 bar2_sz_conf : 1;
      u64 efus_ign : 1;
      u64 nozip : 1;
      u64 raz_11_17 : 7;
      u64 pll_alt_matrix : 1;
      u64 pll_bwadj_denom : 2;
      u64 chip_id : 8;
  #else;
      u64 chip_id : 8;
      u64 pll_bwadj_denom : 2;
      u64 pll_alt_matrix : 1;
      u64 raz_11_17 : 7;
      u64 nozip : 1;
      u64 efus_ign : 1;
      u64 bar2_sz_conf : 1;
      u64 zip_info : 5;
      u64 raz_26_39 : 14;
      u64 efus_lck : 3;
      u64 raz_43_52 : 10;
      u64 pll_half_dis : 1;
      u64 pll_mul : 3;
      u64 raz_57_63 : 7;
  #endif;
    };
 };

okay so it's a u64 (value) or a bitfield struct living in the same spot — union classic. the bitfield order flips depending on whether __BIG_ENDIAN_BITFIELD is defined, and yes, the two branches list the fields in mirror order. icon behavior honestly. 🪞✨

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🦋 Members 🦋

first up, the anonymous one:

• {unnamed_struct} — anonymous. it's giving mysterious. no name, all main character energy. 🫶

💜 the __BIG_ENDIAN_BITFIELD branch, in order:

• pll_mul — main clock PLL multiplier hardware limit
• pll_half_dis — main clock PLL control
• efus_lck — efuse lockdown
• zip_info — ZIP information
• bar2_sz_conf — when zero, BAR2 size conforms to PCIe specification
• efus_ign — efuse ignore
• nozip — ZIP disable
• pll_alt_matrix — select alternate PLL matrix
• pll_bwadj_denom — select CLKF denominator for BWADJ value
• chip_id — chip ID

🍓 the #else branch, in order:

• chip_id — chip ID
• pll_bwadj_denom — select CLKF denominator for BWADJ value
• pll_alt_matrix — select alternate PLL matrix
• nozip — ZIP disable
• efus_ign — efuse ignore
• bar2_sz_conf — when zero, BAR2 size conforms to PCIe specification
• zip_info — ZIP information
• efus_lck — efuse lockdown
• pll_half_dis — main clock PLL control
• pll_mul — main clock PLL multiplier hardware limit

and yes, every single one of those appears twice in the original because of the two branches — so it appears twice here too. no cap, no shortcuts. 💀

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🔥 SEE ALSO 🔥

kernel file: ./drivers/crypto/cavium/nitrox/nitrox_csr.h — that's where this union actually lives, bestie. 🧚

• union ucd_core_eid_ucode_block_num(9)
• union aqm_grp_execmsk_lo(9)
• union aqm_grp_execmsk_hi(9)
• union aqmq_drbl(9)
• union aqmq_qsz(9)
• union aqmq_cmp_thr(9)
• union aqmq_cmp_cnt(9)
• union aqmq_en(9)
• union aqmq_activity_stat(9)
• union emu_fuse_map(9)
• union emu_se_enable(9)
• union emu_ae_enable(9)
• union emu_wd_int_ena_w1s(9)
• union emu_ge_int_ena_w1s(9)
• union nps_pkt_slc_ctl(9)
• union nps_pkt_slc_cnts(9)
• union nps_pkt_slc_int_levels(9)
• union nps_pkt_in_done_cnts(9)
• union nps_pkt_in_instr_ctl(9)
• union nps_pkt_in_instr_rsize(9)
• union nps_pkt_in_instr_baoff_dbell(9)
• union nps_core_int_ena_w1s(9)
• union nps_core_gbl_vfcfg(9)
• union nps_core_int_active(9)
• union efl_core_int(9)
• union efl_core_int_ena_w1s(9)
• union efl_rnm_ctl_status(9)
• union bmi_ctl(9)
• union bmi_int_ena_w1s(9)
• union bmo_ctl2(9)
• union pom_int_ena_w1s(9)
• union lbc_inval_ctl(9)
• union lbc_int_ena_w1s(9)
• union lbc_int(9)
• union lbc_inval_status(9)
• union rst_boot(9)

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reminder bestie: the fields are bitfields — the raz_* ones are just reserved bits sitting there being quiet. don't go assigning meaning to them, that's not the vibe. 🙈

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okay that's the whole page, go drink some water and read a union. 💖

./drivers/crypto/cavium/nitrox · October 2026 · union fus_dat1(9) — mwah, signed, sealed, slayed. 💅✨🦋