STRUCT ZL3073X_HWREG_SEQ_ITEM(9)
πΈ NAME πΈ
okay bestie, welcome to the struct zl3073x_hwreg_seq_item(9) page in the Kernel API Manual β¨ this one is literally all about struct zl3073x_hwreg_seq_item β the HW register write sequence item π
no cap.
β¨ SYNOPSIS β¨
hereβs the struct in all its main-character glory, copied exactly:
struct zl3073x_hwreg_seq_item {
u32 addr;
u32 value;
u32 mask;
u32 wait;
};
π Members π
vibe check on the fields, because every single one is doing its job:
addrβ HW register to be written β yes bestie, this is the register getting the write πvalueβ value to be written to HW register β the value going into that register β¨maskβ bitmask indicating bits to be updated β it tells you which bits are getting the update πwaitβ number of ms to wait after register write β literally the wait time after the write, in ms β³
π¦ SEE ALSO π¦
go give these besties a look too, iykyk π:
- Kernel file:
./drivers/dpll/zl3073x/core.h struct zl3073x_chip_info(9)struct zl3073x_dev(9)zl3073x_dev_is_ref_phase_comp_32bit(9)zl3073x_input_pin_ref_get(9)zl3073x_output_pin_out_get(9)zl3073x_dev_ref_freq_get(9)zl3073x_dev_ref_is_diff(9)zl3073x_dev_synth_freq_get(9)zl3073x_dev_out_synth_get(9)zl3073x_dev_out_is_enabled(9)zl3073x_dev_out_is_stepped(9)zl3073x_dev_out_dpll_get(9)zl3073x_dev_output_pin_freq_get(9)zl3073x_dev_out_is_diff(9)zl3073x_dev_output_pin_is_enabled(9)
and thatβs the tea β this page comes from the ./drivers/dpll/zl3073x source/version, October 2026 edition β slay ππ«Ά
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms