STRUCT XILINX_CPM_PCIE(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’… NAME πŸ’…

struct xilinx_cpm_pcie β€” bestie, it's literally the PCIe port information struct, that's the whole vibe ✨


πŸ¦‹ SYNOPSIS πŸ¦‹

Okay so picture this: you're in the Kernel API Manual, and this is the struct you came for πŸ‘‘

struct xilinx_cpm_pcie {
    struct device                   *dev;
    void __iomem                    *reg_base;
    void __iomem                    *cpm_base;
    struct irq_domain               *intx_domain;
    struct irq_domain               *cpm_domain;
    struct pci_config_window        *cfg;
    int intx_irq;
    int irq;
    raw_spinlock_t lock;
    const struct xilinx_cpm_variant   *variant;
 };
No cap, that field list is exact β€” don't be out here renaming anything, the compiler will NOT be your friend πŸ’€

πŸŽ€ MEMBERS πŸŽ€

Every single one of them, in order, we're not skipping a thing 🫢

  • dev β€” the device pointer, aka the main character reference 🌟
  • reg_base β€” Bridge Register Base, that's where the registers live 🏠
  • cpm_base β€” CPM System Level Control and Status Register(SLCR) Base β€” say it with your chest, SLCR πŸ’œ
  • intx_domain β€” legacy IRQ domain pointer, the old-school one πŸŽ€
  • cpm_domain β€” CPM IRQ domain pointer, the CPM-flavoured one πŸ¦‹
  • cfg β€” holds mappings of config space window, like a little window into config space πŸͺŸ
  • intx_irq β€” legacy interrupt number πŸ”’
  • irq β€” Error interrupt number, that's a different number, don't mix them up πŸ™ˆ
  • lock β€” lock protecting shared register access, guards the shared registers with its life πŸ’…
  • variant β€” CPM version check pointer, so you know which CPM you're dealing with πŸ‘‘

✨ SEE ALSO ✨

Go read these next, they're all iconic πŸ’–


And that's the page, bestie 🫢 sign-off time: this came from ./drivers/pci/controller and it's dated October 2026, struct xilinx_cpm_pcie(9), periodt β­πŸ’œ

πŸ“¦ where this page comes from