STRUCT XE_TILE(9)

💅 struct xe_tile(9) — the tea on your hardware tile

okay so bestie, buckle up 🎀 this is the struct xe_tile page from the Kernel API Manual, and it's literally the blueprint of what a "tile" even is. no cap.

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✨ SYNOPSIS ✨

here's the whole shape of it, verbatim, because we do not paraphrase struct layouts in this house 💖

struct xe_tile {
    struct xe_device *xe;
    u8 id;
    struct xe_gt *primary_gt;
    struct xe_gt *media_gt;
    struct xe_mmio mmio;
    struct {
      struct xe_vram_region *kernel_vram;
      struct xe_vram_region *vram;
      struct xe_ggtt *ggtt;
      struct xe_sa_manager *kernel_bb_pool;
      struct xe_sa_manager *reclaim_pool;
    } mem;
    union {
      struct {
        struct xe_lmtt lmtt;
      } pf;
      struct {
        struct xe_tile_sriov_vf_selfconfig self_config;
      } vf;
    } sriov;
    struct xe_memirq memirq;
    struct work_struct csc_hw_error_work;
    struct {
      struct mutex lock;
    } pcode;
    struct xe_migrate *migrate;
    struct kobject *sysfs;
    struct dentry *debugfs;
    struct xe_mert mert;
 };

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🌸 Members 🌸

• xe — backpointer to the tile's PCI device. it's giving "who's your parent" energy 👑
• id — the ID of the tile. that's it, that's the field.
• primary_gt — the Primary GT.
• media_gt — the Media GT.

heads up bestie: this one is only present on devices with media version >= 13. so no, you can't just assume it's there 😭

• mmio — MMIO info for a tile.

lowkey the layout is kinda iconic: each tile gets its own 16MB space in BAR0, laid out like this 🗺️

• 0-4MB: registers
• 4MB-8MB: reserved
• 8MB-16MB: global GTT

• mem — memory management info for tile. and it's got sub-characters, so let's meet the cast 🫶
  • mem.kernel_vram — kernel-dedicated VRAM info for tile.

even though VRAM is associated with a specific tile, it can still be accessed by all tiles' GTs. so nobody's gatekeeping 💅

• mem.vram — general purpose VRAM info for tile.

same deal, fr fr: although VRAM is associated with a specific tile, it can still be accessed by all tiles' GTs.

• mem.ggtt — Global graphics translation table.
• mem.kernel_bb_pool — pool from which batchbuffers are allocated.

the Media GT shares a pool with its primary GT. sharing is caring ✨

• mem.reclaim_pool — pool for PRLs allocated.

only the main GT has page reclaim list allocations. main character energy only 😤

• sriov — tile level virtualization data. it's a union, so it's a pick one situation:
  • sriov.pf.lmtt — Local Memory Translation Table.
  • sriov.vf.self_config — VF configuration data.
• memirq — Memory Based Interrupts.
• csc_hw_error_work — worker to report CSC HW errors. doing the lord's work 🧚
• pcode — tile's PCODE.
  • pcode.lock — protecting tile's PCODE mailbox data. don't touch without the lock, that's the rule 🙈
• migrate — Migration helper for vram blits and clearing.
• sysfs — sysfs' kobj used by xe_tile_sysfs.
• debugfs — debugfs directory associated with this tile.
• mert — MERT-related data.

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🔥 Description 🔥

so from a driver perspective, a "tile" is effectively a complete GPU — it's got an SGunit, 1-2 GTs, and (for discrete platforms) VRAM. yes, a whole GPU. inside the struct. obsessed 🎀

Multi-tile platforms effectively bundle multiple GPUs behind a single PCI device, and they designate one "root" tile as being responsible for external PCI communication. one tile to talk to the outside world, the rest just vibe ✨

PCI BAR0 exposes the GGTT and MMIO register space for each tile in a stacked layout, and PCI BAR2 exposes the local memory associated with each tile similarly. stacked, not blended 🍓

Device-wide interrupts can be enabled/disabled at the root tile, and the MSTR_TILE_INTR register will report which tiles have interrupts that need servicing. so if something's acting up, that's your vibe check 💀

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🌈 SEE ALSO 🌈

• Kernel file ./drivers/gpu/drm/xe/xe_tile_types.h

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and that's the post 🫶 straight from ./drivers/gpu/drm/xe, October 2026 — go read xe_tile_types.h if you want the raw lore, ily, bye 💜