STRUCT XE_GT(9)

💖 struct xe_gt(9) 💖

okay so this is from the Kernel API Manual, and it's the whole entire teardown of struct xe_gt — buckle up bestie, it's a big one 🎀

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✨ NAME ✨

struct xe_gt — a "Graphics Technology" unit of the GPU. yes that's literally the name. it's giving main character energy and honestly? deserved 👑

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🌸 SYNOPSIS 🌸

struct xe_gt {
    struct xe_tile *tile;
    struct {
      enum xe_gt_type type;
      u32 reference_clock;
      u32 timestamp_base;
      u64 engine_mask;
      u32 gmdid;
      u16 multi_queue_engine_class_mask;
      u8 id;
      u8 has_indirect_ring_state:1;
      u8 has_uncorrectable_error_reporting:1;
      u8 has_xe2_blt_instructions:1;
      u8 num_geometry_xecore_fuse_regs;
      u8 num_compute_xecore_fuse_regs;
    } info;
  #if IS_ENABLED(CONFIG_DEBUG_FS);
    struct xe_gt_stats __percpu *stats;
  #endif;
    struct xe_mmio mmio;
    struct {
      struct xe_force_wake fw;
    } pm;
    union {
      struct xe_gt_sriov_pf pf;
      struct xe_gt_sriov_vf vf;
    } sriov;
    struct xe_reg_sr reg_sr;
    struct {
      struct work_struct worker;
    } reset;
    struct xe_tlb_inval tlb_inval;
    u32 ccs_mode;
    struct {
      struct xe_sa_manager *bb_pool;
      struct xe_hw_engine *paging_hwe0;
      u32 paging_logical_mask;
    } usm;
    struct workqueue_struct *ordered_wq;
    struct xe_uc uc;
    struct xe_gt_idle gtidle;
    const struct xe_exec_queue_ops *exec_queue_ops;
    const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX];
    struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX];
    void *default_lrc[XE_ENGINE_CLASS_MAX];
    struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES];
    struct xe_hw_engine_class_intf  eclass[XE_ENGINE_CLASS_MAX];
    struct kobject *sysfs;
    struct kobject *freq;
    struct {
      u8 uc_index;
      u8 wb_index;
    } mocs;
    struct {
      xe_dss_mask_t g_dss_mask;
      xe_dss_mask_t c_dss_mask;
      xe_eu_mask_t eu_mask_per_dss;
      xe_l3_bank_mask_t l3_bank_mask;
      enum xe_gt_eu_type eu_type;
    } fuse_topo;
    struct {
      const struct xe_mmio_range *ranges;
      u16 group_target;
      u16 instance_target;
      bool initialized;
    } steering[NUM_STEERING_TYPES];
    unsigned int steering_dss_per_grp;
    spinlock_t mcr_lock;
    spinlock_t global_invl_lock;
    struct {
      unsigned long *gt;
      unsigned long *engine;
      unsigned long *lrc;
      unsigned long *oob;
      bool oob_initialized;
    } wa_active;
    struct {
      unsigned long *gt;
      unsigned long *engine;
      unsigned long *lrc;
    } tuning_active;
    struct {
      u64 mask;
      u8 instances_per_class[XE_ENGINE_CLASS_MAX];
    } user_engines;
    struct xe_oa_gt oa;
    struct xe_eu_stall_gt *eu_stall;
  };

like, look at her. so many fields. she's full of secrets 💅

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🦋 Members 🦋

okay we're going through every single one, no skipping, i promised 🫶

• tile — backpointer to GT's tile. she knows where she came from fr fr.
• info — the GT info bundle ✨
• info.type — the type of GT
• info.reference_clock — clock frequency
• info.timestamp_base — the GT timestamp base
• info.engine_mask — mask of engines present on GT. heads up tho: some of them may be reserved in runtime and not available for user. see user_engines.mask (it's the honest one)
• info.gmdid — raw GMD_ID value straight from hardware, no filter no edits
• info.multi_queue_engine_class_mask — bitmask of engine classes with multi queue support enabled
• info.id — unique ID of this GT within the PCI Device. she's the only one of her 💖
• info.has_indirect_ring_state — GT has indirect ring state support
• info.has_uncorrectable_error_reporting — GT has uncorrectable error reporting support
• info.has_xe2_blt_instructions — GT supports Xe2-style MEM_SET and MEM_COPY blitter functionality. ⚠️ and note this: despite the name, some Xe1 platforms may also support this "Xe2-style" feature. the name is a lie, the feature is real, iykyk
• info.num_geometry_xecore_fuse_regs — number of 32b-bit fuse registers the geometry XeCore mask spans. (yes, "32b-bit". i'm copying it exactly, don't come for me 😭)
• info.num_compute_xecore_fuse_regs — number of 32b-bit fuse registers the compute XeCore mask spans
• stats — GT stats. only exists when CONFIG_DEBUG_FS is enabled, she's conditional 🎀
• mmio — mmio info for GT. all GTs within a tile share the same register space, but they each get their own copy of GSI registers at a specific offset. sharing is caring but also boundaries ✋
• pm — power management info for GT. the driver uses the GT's "force wake" interface to wake up specific parts of the GT hardware from C6 sleep states and keep the hardware awake while it's being actively used. literally "wake up bestie, we're going hardware" energy
• pm.fw — force wake for GT
• sriov — virtualization data related to GT
• sriov.pf — PF data. valid only if driver is running as PF
• sriov.vf — VF data. valid only if driver is running as VF
• reg_sr — table with registers to be restored on GT init/resume/reset. the "remember this for later" list ✨
• reset — state for GT resets
• reset.worker — the work item so GT resets can be done async, which lets reset code safely flush all code paths
• tlb_inval — TLB invalidation state
• ccs_mode — number of compute engines enabled. allows fixed mapping of available compute slices to compute engines. by default only the first available compute engine is enabled and all available compute slices are allocated to it. one engine, everything, no notes 💀
• usm — unified shared memory state
• usm.bb_pool — pool from which batchbuffers for USM operations (e.g. migrations, fixing page tables) are allocated. a dedicated pool is needed so USM operations don't get blocked behind any user operations which may have resulted in a fault. personal lane, no traffic 🚗💨
• usm.paging_hwe0 — the first designated paging engine. this is some reserved BCS instance used for USM operations (e.g. migrations, fixing page tables)
• usm.paging_logical_mask — logical mask of paging engines. should be densely populated
• ordered_wq — used to serialize GT resets and TDRs. queue discipline, we love to see it
• uc — micro controllers on the GT
• gtidle — idle properties of GT
• exec_queue_ops — submission backend exec queue operations
• ring_ops — ring operations for this hw engine (1 per engine class)
• fence_irq — fence IRQs (1 per engine class)
• default_lrc — default LRC state
• hw_engines — hardware engines on the GT
• eclass — per hardware engine class interface on the GT
• sysfs — sysfs' kobj used by xe_gt_sysfs
• freq — main GT freq sysfs control. turn it up 🔊
• mocs — info
• mocs.uc_index — UC index
• mocs.wb_index — WB index, only used on L3_CCS platforms
• fuse_topo — GT topology reported by fuse registers
• fuse_topo.g_dss_mask — dual-subslices usable by geometry
• fuse_topo.c_dss_mask — dual-subslices usable by compute
• fuse_topo.eu_mask_per_dss — EU mask per DSS
• fuse_topo.l3_bank_mask — L3 bank mask
• fuse_topo.eu_type — type/width of EU stored in fuse_topo.eu_mask_per_dss
• steering — register steering for individual HW units
• steering.ranges — register ranges used for this steering type
• steering.group_target — target to steer accesses to
• steering.instance_target — instance to steer accesses to
• steering.initialized — whether this steering range is initialized
• steering_dss_per_grp — number of DSS per steering group (gslice, cslice, etc.)
• mcr_lock — protects the MCR_SELECTOR register for the duration of a steered operation. don't touch, she's busy 🔒
• global_invl_lock — protects the register for the duration of a global invalidation of l2 cache
• wa_active — keeps track of active workarounds
• wa_active.gt — bitmap with active GT workarounds
• wa_active.engine — bitmap with active engine workarounds
• wa_active.lrc — bitmap with active LRC workarounds
• wa_active.oob — bitmap with active OOB workarounds
• wa_active.oob_initialized — marks oob as initialized to help detect misuse of XE_GT_WA — it can only be called on initialization after OOB WAs have been processed. ⚠️ don't be that guy
• tuning_active — keeps track of active tunings
• tuning_active.gt — bitmap with active GT tunings
• tuning_active.engine — bitmap with active engine tunings
• tuning_active.lrc — bitmap with active LRC tunings
• user_engines — engines present in GT and available to userspace
• user_engines.mask — like info.engine_mask, but only takes into consideration engines available to userspace. the curated list 💅
• user_engines.instances_per_class — aggregates per class the number of engines available to userspace
• oa — oa observation subsystem per gt info
• eu_stall — EU stall counters subsystem per gt info

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👑 Description 👑

so, what is a GT? a GT ("Graphics Technology") is the subset of a GPU primarily responsible for implementing the graphics, compute, and/or media IP. she encapsulates the hardware engines, the programmable execution units, and the GuC 🧚

and like — each GT has its own handling of power management (RC6+forcewake) and its own multicast register steering. independent queen behavior, no cap ✨

a GPU/tile may have a single GT that supplies all graphics, compute, and media functionality — OR — the graphics/compute and media may be split into separate GTs within a tile. either way, she slays 🌈

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💜 SEE ALSO 💜

• Kernel file ./drivers/gpu/drm/xe/xe_gt_types.h — go read it, bestie, it's right there 🫶

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okay that's the whole page!! and for the cute sign-off: this little masterpiece lives down at ./drivers/gpu/drm/xe, dated October 2026 in the Kernel API Manual 💖 go forth and understand your GTs 🎀✨🌸