STRUCT XE_DEVICE(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸŽ€ struct xe_device (9) β€” Kernel API Manual πŸŽ€

okay bestie, welcome to the top-level struct of the Xe device ✨ this is the big one, the main character energy struct, the one everything else lives inside. buckle up, we're going through every single member. no skimming. πŸ’…


🌸 NAME 🌸

struct xe_device β€” literally the top level struct of the Xe device, the whole entire vibe of your GPU in one C struct 🫢


✨ SYNOPSIS ✨

struct xe_device {
    struct drm_device drm;
  #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY);
    struct intel_display *display;
  #endif;
    struct xe_devcoredump devcoredump;
    struct intel_device_info {
      const char *platform_name;
      const char *graphics_name;
      const char *media_name;
      u32 graphics_verx100;
      u32 media_verx100;
      u32 mem_region_mask;
      enum xe_platform platform;
      enum xe_subplatform subplatform;
      u16 devid;
      u8 revid;
      struct xe_step_info step;
      u8 dma_mask_size;
      u8 vram_flags;
      u8 tile_count;
      u8 max_gt_per_tile;
      u8 multi_lrc_mask;
      u8 gt_count;
      u8 vm_max_level;
      u8 va_bits;
      u8 has_access_counter:1;
      u8 has_asid:1;
      u8 has_atomic_enable_pte_bit:1;
      u8 has_cached_pt:1;
      u8 has_device_atomics_on_smem:1;
      u8 has_drm_ras:1;
      u8 has_fan_control:1;
      u8 has_flat_ccs:1;
      u8 has_gsc_nvm:1;
      u8 has_heci_cscfi:1;
      u8 has_heci_gscfi:1;
      u8 has_i2c:1;
      u8 has_late_bind:1;
      u8 has_llc:1;
      u8 has_mbx_power_limits:1;
      u8 has_mbx_thermal_info:1;
      u8 has_mem_copy_instr:1;
      u8 has_mert:1;
      u8 has_page_reclaim_hw_assist:1;
      u8 has_pre_prod_wa:1;
      u8 has_pxp:1;
      u8 has_ctx_tlb_inval:1;
      u8 has_range_tlb_inval:1;
      u8 has_soc_remapper_sysctrl:1;
      u8 has_soc_remapper_telem:1;
      u8 has_sriov:1;
      u8 has_sysctrl:1;
      u8 has_usm:1;
      u8 has_64bit_timestamp:1;
      u8 is_dgfx:1;
      u8 needs_scratch:1;
      u8 probe_display:1;
      u8 skip_guc_pc:1;
      u8 skip_pcode:1;
      u8 needs_shared_vf_gt_wq:1;
    } info;
    struct {
      unsigned long *oob;
      bool oob_initialized;
    } wa_active;
    struct xe_survivability survivability;
    struct {
      spinlock_t lock;
      atomic_t enabled;
      struct {
        u16 nvec;
        struct xarray indexes;
      } msix;
    } irq;
    struct ttm_device ttm;
    struct {
      size_t size;
      void __iomem *regs;
    } mmio;
    struct {
      struct xe_vram_region *vram;
      struct ttm_resource_manager sys_mgr;
      struct xe_shrinker *shrinker;
      struct xe_ttm_stolen_mgr *stolen_mgr;
    } mem;
    struct {
      enum xe_sriov_mode __mode;
      union {
        struct xe_device_pf pf;
        struct xe_device_vf vf;
      };
      struct workqueue_struct *wq;
    } sriov;
    struct {
      struct xarray asid_to_vm;
      u32 next_asid;
      struct rw_semaphore lock;
      struct workqueue_struct *pf_wq;
  #define XE_PAGEFAULT_QUEUE_COUNT        4;
      struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT];
  #if IS_ENABLED(CONFIG_DRM_XE_PAGEMAP);
      struct drm_pagemap_shrinker *dpagemap_shrinker;
  #endif;
    } usm;
    struct {
      spinlock_t lock;
      struct {
        struct list_head kernel_bo_present;
        struct list_head evicted;
      } early;
      struct {
        struct list_head kernel_bo_present;
        struct list_head evicted;
        struct list_head external;
      } late;
    } pinned;
    wait_queue_head_t ufence_wq;
    struct workqueue_struct *preempt_fence_wq;
    struct workqueue_struct *ordered_wq;
    struct workqueue_struct *unordered_wq;
    struct workqueue_struct *destroy_wq;
    struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE];
    struct {
      struct {
        struct mutex lock;
        struct list_head list;
      } vram_userfault;
    } mem_access;
    struct {
      const struct xe_pat_ops *ops;
      const struct xe_pat_table_entry *table;
      int n_entries;
      const struct xe_pat_table_entry *pat_ats;
      const struct xe_pat_table_entry *pat_primary_pta;
      const struct xe_pat_table_entry *pat_media_pta;
      const struct xe_pat_table_entry *pat_primary_tr_pta;
      const struct xe_pat_table_entry *pat_media_tr_pta;
      u16 idx[__XE_CACHE_LEVEL_COUNT];
    } pat;
    struct {
      bool capable;
      bool allowed;
      u32 vram_threshold;
      struct mutex lock;
    } d3cold;
    struct notifier_block pm_notifier;
    struct completion pm_block;
    struct list_head rebind_resume_list;
    struct mutex rebind_resume_lock;
    struct {
      struct mutex lock;
    } pmt;
    struct {
      spinlock_t lock;
      void (*set_telem_region)(struct xe_device *xe, u32 index);
      void (*set_sysctrl_region)(struct xe_device *xe, u32 index);
    } soc_remapper;
    struct task_struct *pm_callback_task;
    struct xe_hwmon *hwmon;
    struct xe_heci_gsc heci_gsc;
    struct intel_dg_nvm_dev *nvm;
    struct xe_late_bind late_bind;
  #ifdef CONFIG_DRM_XE_DEBUG_PAGE_SIZE;
    struct {
      enum xe_page_size_alloc_ctrl_mode mode;
      u32 cur_index;
      struct mutex lock;
    } page_size_alloc_ctrl;
  #endif;
    struct xe_oa oa;
    struct xe_pxp *pxp;
    bool needs_flr_on_fini;
    atomic_t in_reset;
    struct {
      atomic_t flag;
      enum xe_wedged_mode mode;
      unsigned long method;
      bool inconsistent_reset;
    } wedged;
    void *devres_group;
    struct xe_bo_dev {
      struct work_struct async_free;
      struct llist_head async_list;
    } bo_device;
    struct xe_pmu pmu;
    struct xe_drm_ras ras;
    struct xe_i2c *i2c;
    struct xe_sysctrl sc;
    u32 atomic_svm_timeslice_ms;
    u32 min_run_period_lr_ms;
    u32 min_run_period_pf_ms;
  #ifdef TEST_VM_OPS_ERROR;
    u8 vm_inject_error_position;
  #endif;
  #if IS_ENABLED(CONFIG_TRACE_GPU_MEM);
    atomic64_t global_total_pages;
  #endif;
    struct xe_validation_device val;
    struct {
      struct xe_bo *capture_obj[XE_MAX_TILES_PER_DEVICE + 1];
      u8 region_mask;
    } psmi;
  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST);
    u32 *g2g_test_array;
    atomic_t g2g_test_count;
  #endif;
};

πŸ‘‘ Members πŸ‘‘

okay so now we go field by field, and yes, there are a LOT of them, but that's the whole point β€” no cap, every single one matters πŸ’–

  • drm β€” the actual drm device. the foundation bestie, everything else sits on top of it.
  • display β€” display device data πŸ–₯️ and here's the tea: it must be placed after the drm device member. not optional. don't move it.
  • devcoredump β€” device coredump. the receipts when things go sideways πŸ’€
  • info β€” device info. the giant nested struct of everything this device is.

πŸ” info.* β€” the identity section πŸ”

  • info.platform_name β€” platform name
  • info.graphics_name β€” graphics IP name
  • info.media_name β€” media IP name
  • info.graphics_verx100 β€” graphics IP version
  • info.media_verx100 β€” media IP version
  • info.mem_region_mask β€” mask of valid memory regions
  • info.platform β€” Xe platform enum
  • info.subplatform β€” Xe subplatform enum
  • info.devid β€” device ID
  • info.revid β€” device revision
  • info.step β€” stepping information for each IP
  • info.dma_mask_size β€” DMA address bits
  • info.vram_flags β€” Vram flags
  • info.tile_count β€” Number of tiles 🧱
  • info.max_gt_per_tile β€” Number of GT IDs allocated to each tile
  • info.multi_lrc_mask β€” bitmask of engine classes which support multi-lrc
  • info.gt_count β€” Total number of GTs for entire device
  • info.vm_max_level β€” Max VM level
  • info.va_bits β€” Maximum bits of a virtual address

🌈 info.has_* β€” the giant feature checklist 🌈

these are all single-bit flags, so think of it as the device's little "do I do this? πŸ‘€" list. slay.

  • info.has_access_counter β€” Device supports access counter
  • info.has_asid β€” Has address space ID
  • info.has_atomic_enable_pte_bit β€” Device has atomic enable PTE bit
  • info.has_cached_pt β€” Supports caching pagetable
  • info.has_device_atomics_on_smem β€” Supports device atomics on SMEM
  • info.has_drm_ras β€” Device supports drm_ras (Reliability, Availability, Serviceability)
  • info.has_fan_control β€” Device supports fan control πŸŒ€
  • info.has_flat_ccs β€” Whether flat CCS metadata is used
  • info.has_gsc_nvm β€” Device has gsc non-volatile memory
  • info.has_heci_cscfi β€” device has heci cscfi
  • info.has_heci_gscfi β€” device has heci gscfi
  • info.has_i2c β€” Device has I2C controller
  • info.has_late_bind β€” Device has firmware late binding support
  • info.has_llc β€” Device has a shared CPU+GPU last level cache
  • info.has_mbx_thermal_info β€” Device supports thermal mailbox commands 🌑️
  • info.has_mem_copy_instr β€” Device supports MEM_COPY instruction
  • info.has_mert β€” Device has standalone MERT
  • info.has_page_reclaim_hw_assist β€” Device supports page reclamation feature
  • info.has_pre_prod_wa β€” Pre-production workarounds still present in driver
  • info.has_pxp β€” Device has PXP support
  • info.has_ctx_tlb_inval β€” Has context based TLB invalidations
  • info.has_range_tlb_inval β€” Has range based TLB invalidations
  • info.has_soc_remapper_sysctrl β€” Has SoC remapper system controller
  • info.has_soc_remapper_telem β€” Has SoC remapper telemetry support
  • info.has_sriov β€” Supports SR-IOV
  • info.has_sysctrl β€” Supports System Controller
  • info.has_usm β€” Device has unified shared memory support
  • info.has_64bit_timestamp β€” Device supports 64-bit timestamps ⏱️
  • info.is_dgfx β€” is discrete device
  • info.needs_scratch β€” needs scratch page for oob prefetch to work
  • info.probe_display β€” Probe display hardware. If set to false, the driver will behave as if there is no display hardware present and will not try to read/write to it in any way. The display hardware, if it exists, will not be exposed to userspace and will be left untouched in whatever state the firmware or bootloader left it in. πŸ™ˆ (<- literally "we pretend it isn't there and we do not touch it")
  • info.skip_guc_pc β€” Skip GuC based PM feature init
  • info.skip_pcode β€” skip access to PCODE uC
  • info.needs_shared_vf_gt_wq β€” needs shared GT WQ on VF

🫢 wa_active β€” keeping the receipts 🫢

  • wa_active β€” keep track of active workarounds
  • wa_active.oob β€” bitmap with active OOB workarounds

πŸ’… and that's where part 1 lands β€” mid-struct, mid-vibe, exactly as the page was written. the rest is still coming, don't you dare close the tab πŸŽ€
  • wa_active.oob_initialized β€” marks oob as initialized, and the whole point of that is helping detect misuse of XE_DEVICE_WA β€” lowkey it can only be called on initialization after the Device OOB WAs have been processed 😌
  • survivability β€” survivability information for device 🫢

okay next up, the interrupt corner, it's giving very "don't touch my stuff" energy ✨

  • irq β€” device interrupt state
  • irq.lock β€” lock for processing irq's on this device
  • irq.enabled β€” interrupts enabled on this device
  • irq.msix β€” irq info for platforms that support MSI-X
  • irq.msix.nvec β€” number of MSI-X interrupts
  • irq.msix.indexes β€” used to allocate MSI-X indexes
  • ttm β€” ttm device

memory stuff, we love a memory moment πŸ’…

  • mmio β€” mmio info for device
  • mmio.size β€” size of MMIO space for device
  • mmio.regs β€” pointer to MMIO space for device
  • mem β€” memory info for device
  • mem.vram β€” VRAM info for device
  • mem.sys_mgr β€” system TTM manager
  • mem.shrinker β€” system memory shrinker.
  • mem.stolen_mgr β€” stolen memory manager.

  • sriov β€” device level virtualization data
  • sriov.__mode β€” SR-IOV mode (don't access directly! seriously, hands off πŸ™ˆ)
  • {unnamed_union} β€” anonymous
  • sriov.pf β€” PF specific data
  • sriov.vf β€” VF specific data
  • sriov.wq β€” workqueue used by the virtualization workers

unified memory state, main character energy tbh πŸ‘‘

  • usm β€” unified memory state
  • usm.asid_to_vm β€” convert an ASID to VM
  • usm.next_asid β€” next ASID, used to cyclical alloc asids
  • usm.lock β€” protects UM state
  • usm.pf_wq β€” page fault work queue, unbound, high priority πŸ”₯
  • usm.pf_queue β€” page fault queues
  • usm.dpagemap_shrinker β€” shrinker for unused pagemaps

pinned BOs, the way these are split into early and late is so organized of them πŸŽ€

  • pinned β€” pinned BO state
  • pinned.lock β€” protected pinned BO list state
  • pinned.early β€” early pinned lists
  • pinned.early.kernel_bo_present β€” pinned kernel BO that are present
  • pinned.early.evicted β€” pinned BO that have been evicted
  • pinned.late β€” late pinned lists
  • pinned.late.kernel_bo_present β€” pinned kernel BO that are present
  • pinned.late.evicted β€” pinned BO that have been evicted
  • pinned.late.external β€” pinned external and dma-buf.

a whole little family of workqueues, iykyk ⭐

  • ufence_wq β€” user fence wait queue
  • preempt_fence_wq β€” used to serialize preempt fences
  • ordered_wq β€” used to serialize compute mode resume
  • unordered_wq β€” used to serialize unordered work
  • destroy_wq β€” used to serialize SVM pagemap destroy work

  • tiles β€” device tiles
  • mem_access β€” keep track of memory access in the device, possibly triggering additional actions when they occur.
  • mem_access.vram_userfault β€” encapsulate vram_userfault related stuff
  • mem_access.vram_userfault.lock β€” protects access to mem_access.vram_userfault.list. Using mutex instead of spinlock as lock is applied to entire list operation which may sleep 😴
  • mem_access.vram_userfault.list β€” keep list of userfaulted vram bo, which require to release their mmap mappings at runtime suspend path

PAT time, and yes there are a lot of entries, we're listing them all bestie πŸ’œ

  • pat β€” encapsulate PAT related stuff
  • pat.ops β€” internal operations to abstract platforms
  • pat.table β€” PAT table to program in the HW
  • pat.n_entries β€” number of PAT entries
  • pat.pat_ats β€” PAT entry for PCIe ATS responses
  • pat.pat_primary_pta β€” primary GT PAT entry for page table accesses
  • pat.pat_media_pta β€” media GT PAT entry for page table accesses
  • pat.pat_primary_tr_pta β€” primary GT PAT entry for TRTT page table accesses
  • pat.pat_media_tr_pta β€” media GT PAT entry for TRTT page table accesses

d3cold corner ❄️

  • d3cold β€” encapsulate d3cold related stuff
  • d3cold.capable β€” indicates if root port is d3cold capable
  • d3cold.allowed β€” indicates if d3cold is a valid device state
  • d3cold.vram_threshold β€” this represents the permissible threshold (in megabytes) for vram save/restore. d3cold will be disallowed, when vram_usages is above or equals the threshold value to avoid the vram save/restore latency. Default threshold value is 300mb.
  • d3cold.lock β€” protect vram_threshold

  • pm_notifier β€” our PM notifier to perform actions in response to various PM events.
  • pm_block β€” completion to block validating tasks on suspend / hibernate prepare
  • rebind_resume_list β€” list of wq items to kick on resume.
  • rebind_resume_lock β€” lock to protect the rebind_resume_list
  • pmt β€” support the PMT driver callback interface
  • pmt.lock β€” protect access for telemetry data

SoC remapper, say that five times fast πŸ¦‹

  • soc_remapper β€” SoC remapper object
  • soc_remapper.lock β€” serialize access to SoC Remapper's index registers
  • soc_remapper.set_telem_region β€” set telemetry index
  • soc_remapper.set_sysctrl_region β€” set system controller index

  • pm_callback_task β€” track the active task that is running in either the runtime_suspend or runtime_resume callbacks.
  • hwmon β€” hwmon subsystem integration
  • heci_gsc β€” graphics security controller
  • nvm β€” discrete graphics non-volatile memory
  • late_bind β€” xe mei late bind interface
  • page_size_alloc_ctrl β€” user BO page-size allocation debug control state
  • page_size_alloc_ctrl.mode β€” xe page size allocation control mode
  • page_size_alloc_ctrl.cur_index β€” round-robin index used by mixed mode
  • page_size_alloc_ctrl.lock β€” protects mode and cur_index
  • oa β€” oa observation subsystem
  • pxp β€” encapsulate Protected Xe Path support

the "something went very wrong" section πŸ”₯

  • needs_flr_on_fini β€” requests function-reset on fini
  • in_reset β€” indicates if device is in reset
  • wedged β€” struct to control Wedged States and mode
  • wedged.flag β€” Xe device faced a critical error and is now blocked. πŸ’€
  • wedged.mode β€” mode controlled by kernel parameter and debugfs
  • wedged.method β€” recovery method to be sent in the drm device wedged uevent
  • wedged.inconsistent_reset β€” inconsistent reset policy state between GTs

  • devres_group β€” devres group
  • bo_device β€” struct to control async free of BOs
  • bo_device.async_free β€” free worker
  • bo_device.async_list β€” list of BOs to be freed
  • pmu β€” performance monitoring unit
  • ras β€” RAS structure for device
  • i2c β€” I2C host controller
  • sc β€” System Controller

timing + debug bits, lil guys but important πŸ“

  • atomic_svm_timeslice_ms β€” atomic SVM fault timeslice MS
  • min_run_period_lr_ms β€” LR VM (preempt fence mode) timeslice
  • min_run_period_pf_ms β€” LR VM (page fault mode) timeslice
  • vm_inject_error_position β€” inject errors at different places in VM bind IOCTL based on this value
  • global_total_pages β€” global GPU page usage tracked for gpu_mem tracepoints
  • val β€” the domain for exhaustive eviction, which is currently per device.
  • psmi β€” GPU debugging via additional validation HW
  • psmi.capture_obj β€” PSMI buffer for VRAM
  • psmi.region_mask β€” mask of valid memory regions
  • g2g_test_array β€” for testing G2G communications
  • g2g_test_count β€” for testing G2G communications

🌈 SEE ALSO 🌈

  • Kernel file ./drivers/gpu/drm/xe/xe_device_types.h enum
  • xe_wedged_mode(9), enum xe_page_size_alloc_ctrl_mode(9), struct xe_file(9)
go read those too bestie, they're literally right there and they slay πŸ’…

and that's the whole struct, no cap 🫢 this lil page lives at ./drivers/gpu/drm/xe, dated October 2026, and it's officially titled struct xe_device(9) β€” mwah, bye ✨

πŸ“¦ where this page comes from