STRUCT TEGRA_SDMMC_MUX(9)

🦋 struct tegra_sdmmc_mux(9) 🦋

okay bestie, welcome to the Kernel API Manual page for struct tegra_sdmmc_mux(9) — yes, the manual name is folded in right here, all cute and accounted for. this is the tea on the switch divider with Low Jitter inputs for SDMMC. ✨

✨ NAME ✨

struct tegra_sdmmc_mux — the switch divider with Low Jitter inputs for SDMMC. that's the whole vibe: it's a switch divider, it's got Low Jitter inputs, and it's for SDMMC. periodt. 💅

🌸 SYNOPSIS 🌸

struct tegra_sdmmc_mux {
    struct clk_hw           hw;
    void __iomem            *reg;
    spinlock_t *lock;
    const struct clk_ops    *gate_ops;
    struct tegra_clk_periph_gate    gate;
    u8 div_flags;
 };

🎀 Members 🎀

• hw — the handle between common and hardware-specific interfaces. it's giving bridge energy 🫶
• reg — the register controlling mux and divider. iconic.
• lock — optional register lock. optional, bestie — don't assume it's always there.
• gate_ops — gate clock ops.
• gate — gate clock.

also chillin' in the synopsis: u8 div_flags; — the original Members list doesn't give it a separate blurb, so no invented lore here. 🙈

🌈 SEE ALSO 🌈

Kernel file: ./drivers/clk/tegra/clk.h

• struct tegra_clk_sync_source(9)
• struct tegra_clk_frac_div(9)
• struct tegra_clk_pll_freq_table(9)
• struct pdiv_map(9)
• struct div_nmp(9)
• struct tegra_clk_pll_params(9)
• struct tegra_clk_pll(9)
• struct tegra_audio_clk_info(9)
• struct tegra_clk_pll_out(9)
• struct tegra_clk_periph_regs(9)
• struct tegra_clk_periph_gate(9)

xoxo, bestie — signed off from the source ./drivers/clk/tegra, dated October 2026 💖