STRUCT TEGRA_PINCTRL_SOC_DATA(9)

๐Ÿ“ฆ version 7.3.1, in nixpkgs unstable

๐Ÿ’… struct tegra_pinctrl_soc_data(9) โ€” Kernel API Manual ๐ŸŽ€

okay bestie, welcome to the glow-up doc for struct tegra_pinctrl_soc_data โ€” it's the config blueprint for the Tegra pin controller driver, and honestly? it's giving "quietly runs the whole show" energy ๐Ÿ‘‘


โœจ NAME โœจ

struct tegra_pinctrl_soc_data โ€” the Tegra pin controller driver configuration ๐Ÿฆ‹


๐ŸŒธ SYNOPSIS ๐ŸŒธ

struct tegra_pinctrl_soc_data {
    unsigned ngpios;
    const char *gpio_compatible;
    const struct pinctrl_pin_desc *pins;
    unsigned npins;
    const char * const *functions;
    unsigned nfunctions;
    const struct tegra_pingroup *groups;
    unsigned ngroups;
    bool hsm_in_mux;
    bool schmitt_in_mux;
    bool drvtype_in_mux;
    bool sfsel_in_mux;
 };

like, look at her. every field accounted for, no notes ๐Ÿ’–


๐ŸŒˆ Members ๐ŸŒˆ

  • ngpios โ€” how many GPIO pins the pin controller HW actually touches. the headcount, basically ๐Ÿงฎ
  • gpio_compatible โ€” the device-tree GPIO compatible string. her official government name โœจ
  • pins โ€” an array describing all the pins the pin controller affects. โš ๏ธ and here's the rule, no cap: all pins which are also GPIOs must be listed first within the array, and be numbered identically to the GPIO controller's numbering. so like, order matters, bestie. don't be chaotic with it ๐Ÿซถ
  • npins โ€” the number of entries in pins. the count ๐ŸŒธ
  • functions โ€” an array describing all the mux functions the SoC supports. the whole menu ๐Ÿ’…
  • nfunctions โ€” the number of entries in functions. menu length, fr fr ๐Ÿ”ข
  • groups โ€” an array describing all the pin groups the pin SoC supports. squad goals, grouped up ๐Ÿ‘ฏ
  • ngroups โ€” the number of entries in groups. how many squads ๐ŸŒŸ
  • hsm_in_mux โ€” High-speed mode field. ๐Ÿšจ only applicable to devices with one pin per group. read that twice if you need to ๐Ÿ’€
  • schmitt_in_mux โ€” Schmitt trigger field. ๐Ÿ˜ญ same deal: only applicable to devices with one pin per group.
  • drvtype_in_mux โ€” Drivetype field. ๐Ÿ”ฅ again โ€” only applicable to devices with one pin per group.
  • sfsel_in_mux โ€” Special function selection field. โญ and yep, only applicable to devices with one pin per group. the four *_in_mux booleans are all matching, it's giving coordinated outfit ๐ŸŽ€
lowkey important: those last four are only for devices with one pin per group. not a vibe check you get to skip ๐Ÿ’œ

๐Ÿฆ‹ SEE ALSO ๐Ÿฆ‹

  • Kernel file ./drivers/pinctrl/tegra/pinctrl-tegra.h struct tegra_function(9), struct tegra_pingroup(9) โ€” go read the whole family, iykyk ๐Ÿ“š

and that's the page!! ๐ŸŽ‰ this masterpiece lives at ./drivers/pinctrl/tegra, dated October 2026 โ€” so she's serving main character energy from the future, and honestly? obsessed. slay, periodt, go configure some pins ๐Ÿ’–โœจ๐Ÿซถ

๐Ÿ“ฆ where this page comes from