STRUCT TEGRA_I2C_HW_FEATURE(9)

💖 struct tegra_i2c_hw_feature(9) 💖

okay so bestie, this is a page straight out of the Kernel API Manual — it's the lowdown on struct tegra_i2c_hw_feature, aka the little struct that tells the Tegra I2C driver what its specific hardware generation can actually do. it's giving "capability checklist but make it a C struct" and honestly? iconic. 🦋

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✨ NAME ✨

struct tegra_i2c_hw_feature — per hardware generation features. like, every Tegra chip's I2C controller is a little different, and this struct is the receipts. 💅

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🌸 SYNOPSIS 🌸

struct tegra_i2c_hw_feature {
    bool has_continue_xfer_support;
    bool has_per_pkt_xfer_complete_irq;
    bool has_config_load_reg;
    u32 clk_divisor_hs_mode;
    u32 clk_divisor_std_mode;
    u32 clk_divisor_fast_mode;
    u32 clk_divisor_fast_plus_mode;
    bool has_multi_master_mode;
    bool has_slcg_override_reg;
    bool has_mst_fifo;
    bool has_mst_reset;
    const struct i2c_adapter_quirks *quirks;
    bool supports_bus_clear;
    bool has_apb_dma;
    u32 tlow_std_mode;
    u32 thigh_std_mode;
    u32 tlow_fast_mode;
    u32 thigh_fast_mode;
    u32 tlow_fastplus_mode;
    u32 thigh_fastplus_mode;
    u32 tlow_hs_mode;
    u32 thigh_hs_mode;
    u32 setup_hold_time_std_mode;
    u32 setup_hold_time_fast_mode;
    u32 setup_hold_time_fastplus_mode;
    u32 setup_hold_time_hs_mode;
    bool has_interface_timing_reg;
    bool enable_hs_mode_support;
    bool has_mutex;
    bool has_fairarb_reg;
    enum tegra_i2c_variant variant;
    const struct tegra_i2c_regs *regs;
 };

look at all those fields. she's thorough. she contains multitudes. 🎀

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👑 Members 👑

🧚 the transfer-behaviour girlies

• has_continue_xfer_support — continue-transfer supported. yes queen, keep going.
• has_per_pkt_xfer_complete_irq — Has enable/disable capability for transfer completion interrupt on per packet basis. so you can toggle that interrupt packet-by-packet, no cap.
• has_config_load_reg — Has the config load register to load the new configuration. new config, who dis 💅
• has_multi_master_mode — The I2C controller supports running in single-master or multi-master mode. choose your fighter.
• quirks — I2C adapter quirks for limiting write/read transfer size and not allowing 0 length transfers. she has boundaries.

⏰ clock divisor besties

• clk_divisor_hs_mode — Clock divisor in HS mode.
• clk_divisor_std_mode — Clock divisor in standard mode. It is applicable if there is no fast clock source i.e. single clock source.
• clk_divisor_fast_mode — Clock divisor in fast mode. It is applicable if there is no fast clock source i.e. single clock source.
• clk_divisor_fast_plus_mode — Clock divisor in fast mode plus. It is applicable if there is no fast clock source (i.e. single clock source).

🌈 registers & hardware flexes

• has_slcg_override_reg — The I2C controller supports a register that overrides the second level clock gating. override? she said i'll allow it.
• has_mst_fifo — The I2C controller contains the new MST FIFO interface that provides additional features and allows for longer messages to be transferred in one go. longer messages, one go — we love efficiency 🙈
• has_mst_reset — The I2C controller contains MASTER_RESET_CTRL register which provides an alternative to controller reset when configured as I2C master. a reset glow-up, if you will ✨
• supports_bus_clear — Bus Clear support to recover from bus hang during SDA stuck low from device for some unknown reasons. the "have you tried turning it off and on again" of I2C, lowkey.
• has_apb_dma — Support of APBDMA on corresponding Tegra chip. dma but make it apb 💜
• has_interface_timing_reg — Has interface timing register to program the tuned timing settings. tuned. tuned. 🔥
• enable_hs_mode_support — Enable support for high speed (HS) mode transfers. go fast, be safe 🦋
• has_mutex — Has mutex register for mutual exclusion with other firmwares or VMs. sharing is caring but the mutex is mandatory.
• has_fairarb_reg — Has fairness arbitration register for SMBUS/MCTP support. fair arbitration = no drama in the group chat, periodt.

🫶 timing girlies (low & high periods)

• tlow_std_mode — Low period of the clock in standard mode.
• thigh_std_mode — High period of the clock in standard mode.
• tlow_fast_mode — Low period of the clock in fast mode.
• thigh_fast_mode — High period of the clock in fast mode.
• tlow_fastplus_mode — Low period of the clock in fast-plus mode.
• thigh_fastplus_mode — High period of the clock in fast-plus mode.
• tlow_hs_mode — Low period of the clock in HS mode.
• thigh_hs_mode — High period of the clock in HS mode.

🍓 setup & hold times (start/stop conditions)

• setup_hold_time_std_mode — Setup and hold time for start and stop conditions in standard mode.
• setup_hold_time_fast_mode — Setup and hold time for start and stop conditions in fast mode.
• setup_hold_time_fastplus_mode — Setup and hold time for start and stop conditions in fast-plus mode.
• setup_hold_time_hs_mode — Setup and hold time for start and stop conditions in HS mode.

💫 the "who even am i" fields

• variant — This represents the I2C controller variant. main character identification 🎀
• regs — Register offsets for the specific SoC variant. the actual map to the actual hardware, iykyk.

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🔭 SEE ALSO 🔭

• Kernel file ./drivers/i2c/busses/i2c-tegra.c
• struct tegra_i2c_dev(9)

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bestie note: this page lives in ./drivers/i2c/busses, and it's dated October 2026. yes, the future. we stay ahead 💅

and that's the whole page — struct tegra_i2c_hw_feature(9), straight from the Kernel API Manual, signed off with love. go forth and configure your timing registers, queen 👑✨