STRUCT TEGRA_I2C_DEV(9)
π struct tegra_i2c_dev(9) β the kernel API manual, bestie edition β¨
okay so this page is from the Kernel API Manual, and it's literally all about struct tegra_i2c_dev β the per device I2C context. yes, that's a whole struct of I2C vibes. let's get into it π
π¦ NAME π¦
struct tegra_i2c_dev β per device I2C context. that's it, that's the whole name. main character energy fr.
β¨ SYNOPSIS β¨
here she is in all her glory, no cap, copy-pasted exactly:
struct tegra_i2c_dev {
struct device *dev;
struct i2c_adapter adapter;
const struct tegra_i2c_hw_feature *hw;
unsigned int cont_id;
unsigned int irq;
phys_addr_t base_phys;
void __iomem *base;
struct clk_bulk_data clocks[2];
unsigned int nclocks;
struct clk *div_clk;
struct i2c_timings timings;
struct completion msg_complete;
size_t msg_buf_remaining;
unsigned int msg_len;
int msg_err;
u8 *msg_buf;
struct completion dma_complete;
struct dma_chan *dma_chan;
unsigned int dma_buf_size;
struct device *dma_dev;
dma_addr_t dma_phys;
void *dma_buf;
bool multimaster_mode;
bool is_mctp;
bool atomic_mode;
bool dma_mode;
bool msg_read;
};
look at all those fields π she's stunning. now let's meet every single member one by one, because we do not skip members here π
πΈ Members πΈ
devβ device reference for power management. like the parent who signs the permission slip π«Άadapterβ core I2C layer adapter information. the actual I2C-ness of it all.hwβ Tegra I2C HW feature. the hardware tea βcont_idβ I2C controller ID, used for packet header. literally the controller's name tag π·οΈirqβ IRQ number of transfer complete interrupt. the "we're done here!" buzzer πbase_physβ physical base address of the I2C controller. the real physical address, no fake vibes.baseβ ioremapped registers cookie. yes, the manpage calls it a cookie πͺ iconic honestly.clocksβ array of I2C controller clocks. it's an array, clock besties πnclocksβ number of clocks in the array. gotta know how many clocks are clocking.div_clkβ clock reference for div clock of I2C controller. the divider clock, slaying divider duties.timingsβ i2c timings information like bus frequency. all the timing deets, so punctual β¨msg_completeβ transfer completion notifier. the "message sent!!" notification πmsg_buf_remainingβ size of unsent data in the message buffer. how much message is still waiting to go out π€msg_lenβ length of message in current transfer. the current transfer's message length, periodt.msg_errβ error code for completed message. when the message says "well that happened" πmsg_bufβ pointer to current message data. pointing right at the message data, iykyk.dma_completeβ DMA completion notifier. the DMA version of "we're so back" πdma_chanβ DMA channel. the channel. the DMA one.dma_buf_sizeβ DMA buffer size. how big the DMA buffer is, obviously πdma_devβ DMA device used for transfers. the device doing the DMA transferring.dma_physβ handle to DMA resources. handles to the DMA resources, held gently π«Άdma_bufβ pointer to allocated DMA buffer. pointing at the buffer we allocated, slay.multimaster_modeβ indicates that I2C controller is in multi-master mode. multiple masters, honestly chaotic but we love her πis_mctpβ indicates that the I2C controller is used as an MCTP controller. MCTP mode: active or not, that's the question.atomic_modeβ indicates active atomic transfer. atomic transfer currently active, lowkey powerful βdma_modeβ indicates active DMA transfer. DMA transfer currently active, highkey fast π₯msg_readβ indicates that the transfer is a read access. it's a read!! π
π SEE ALSO π
- Kernel file
./drivers/i2c/busses/i2c-tegra.cstructtegra_i2c_hw_feature(9)
go read those too bestie, they're the supporting cast π
π§ Sign-off π§
this lil page lives in ./drivers/i2c/busses, and the version tag says October 2026 β so yeah, future vibes β¨. mwah, go forth and I2C ππ¦πΈ
π¦ where this page comes from
- nixpkgs unstable: linux-manual 7.3.1
- π girlified by deepseek-ai/DeepSeek-V4.1-Flash-1017 on : a language model's rewrite of the original, under its terms