STRUCT TEGRA_DFLL_SOC_DATA(9)

💜 struct tegra_dfll_soc_data — Kernel API Manual, bestie edition 💜

okay so this is struct tegra_dfll_soc_data(9) straight out of the Kernel API Manual, and it's literally the SoC-specific hook-and-integration situation for the DFLL driver. no cap, that's the whole vibe: it's the little struct that tells the DFLL driver "hey, here's how this particular chip wants to be handled." ✨

🌸 NAME 🌸

struct tegra_dfll_soc_data — SoC-specific hooks/integration for the DFLL driver 🎀

🦋 SYNOPSIS 🦋

struct tegra_dfll_soc_data {
    struct device *dev;
    unsigned long max_freq;
    const struct cvb_table *cvb;
    struct rail_alignment alignment;
    void (*init_clock_trimmers)(void);
    void (*set_clock_trimmers_high)(void);
    void (*set_clock_trimmers_low)(void);
 };

it's giving "one struct to rule the SoC integration." 👑

💅 Members 💅

• dev — a struct device * that holds the OPP table for the DFLL. like, the device is the main character that owns the OPP table, iykyk 🫶
• max_freq — the maximum frequency supported on this SoC. that's the ceiling, bestie, the absolute most this chip will do 🔥
• cvb — the CPU frequency table for this SoC. your whole CVB situation, right here ✨
• alignment — parameters of the regulator step and offset. the nitty-gritty of how the regulator lines up, lowkey important 💖
• init_clock_trimmers — callback to initialize clock trimmers. gotta set them up first, obviously 🌸
• set_clock_trimmers_high — callback to tune clock trimmers for high voltage. high voltage mode, activated ⚡
• set_clock_trimmers_low — callback to tune clock trimmers for low voltage. and the low voltage counterpart, slay 💜

🌈 SEE ALSO 🌈

Kernel file ./drivers/clk/tegra/clk-dfll.h — go read it, it's right there, fr fr 🦋

anyway that's the whole page, no notes 💅 and yeah, this lil beauty comes from ./drivers/clk/tegra, dated October 2026, in the Kernel API Manual — mwah, bye bestie! 🎀✨😭🫶