STRUCT TEGRA_CLK_PLL_PARAMS(9)

💅 NAME 💅

okay so bestie, welcome to the Kernel API Manual ✨ — this page is all about struct tegra_clk_pll_params, which is literally just PLL parameters. that's it, that's the whole vibe 🎀

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✨ SYNOPSIS ✨

like, here's the whole struct, no cap — every field exactly where it lives:

struct tegra_clk_pll_params {
    unsigned long   input_min;
    unsigned long   input_max;
    unsigned long   cf_min;
    unsigned long   cf_max;
    unsigned long   vco_min;
    unsigned long   vco_max;
    u32 base_reg;
    u32 misc_reg;
    u32 lock_reg;
    u32 lock_mask;
    u32 lock_enable_bit_idx;
    u32 iddq_reg;
    u32 iddq_bit_idx;
    u32 reset_reg;
    u32 reset_bit_idx;
    u32 sdm_din_reg;
    u32 sdm_din_mask;
    u32 sdm_ctrl_reg;
    u32 sdm_ctrl_en_mask;
    u32 ssc_ctrl_reg;
    u32 ssc_ctrl_en_mask;
    u32 aux_reg;
    u32 dyn_ramp_reg;
    u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
    u32 pmc_divnm_reg;
    u32 pmc_divp_reg;
    u32 flags;
    int stepa_shift;
    int stepb_shift;
    int lock_delay;
    int max_p;
    bool defaults_set;
    const struct pdiv_map *pdiv_tohw;
    struct div_nmp  *div_nmp;
    struct tegra_clk_pll_freq_table *freq_table;
    unsigned long   fixed_rate;
    u16 mdiv_default;
    u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
    void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
    int (*calc_rate)(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate);
    unsigned long   (*adjust_vco)(struct tegra_clk_pll_params *pll_params, unsigned long parent_rate);
    void (*set_defaults)(struct tegra_clk_pll *pll);
    int (*dyn_ramp)(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg);
    int (*pre_rate_change)(void);
    void (*post_rate_change)(void);
 };

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🎀 Members 🎀

every single one, bestie, in order, no skips 💖

• input_min — Minimum input frequency
• input_max — Maximum input frequency
• cf_min — Minimum comparison frequency
• cf_max — Maximum comparison frequency
• vco_min — Minimum VCO frequency
• vco_max — Maximum VCO frequency
• base_reg — PLL base reg offset
• misc_reg — PLL misc reg offset
• lock_reg — PLL lock reg offset
• lock_mask — Bitmask for PLL lock status
• lock_enable_bit_idx — Bit index to enable PLL lock
• iddq_reg — PLL IDDQ register offset
• iddq_bit_idx — Bit index to enable PLL IDDQ
• reset_reg — Register offset of where RESET bit is
• reset_bit_idx — Shift of reset bit in reset_reg
• sdm_din_reg — Register offset where SDM settings are
• sdm_din_mask — Mask of SDM divider bits
• sdm_ctrl_reg — Register offset where SDM enable is
• sdm_ctrl_en_mask — Mask of SDM enable bit
• ssc_ctrl_reg — Register offset where SSC settings are
• ssc_ctrl_en_mask — Mask of SSC enable bit
• aux_reg — AUX register offset
• dyn_ramp_reg — Dynamic ramp control register offset
• ext_misc_reg — Miscellaneous control register offsets
• pmc_divnm_reg — n, m divider PMC override register offset (PLLM)
• pmc_divp_reg — p divider PMC override register offset (PLLM)
• flags — PLL flags
• stepa_shift — Dynamic ramp step A field shift
• stepb_shift — Dynamic ramp step B field shift
• lock_delay — Delay in us if PLL lock is not used
• max_p — maximum value for the p divider
• defaults_set — Boolean signaling all reg defaults for PLL set.
• pdiv_tohw — mapping of p divider to register values
• div_nmp — offsets and widths on n, m and p fields
• freq_table — array of frequencies supported by PLL
• fixed_rate — PLL rate if it is fixed
• mdiv_default — Default value for fixed mdiv for this PLL
• round_p_to_pdiv — Callback used to round p to the closed pdiv
• set_gain — Callback to adjust N div for SDM enabled PLL's based on fractional divider value.
• calc_rate — Callback used to change how out of table rates (dividers and multipler) are calculated.
• adjust_vco — Callback to adjust the programming range of the divider range (if SDM is present)
• set_defaults — Callback which will try to initialize PLL registers to sane default values. This is first tried during PLL registration, but if the PLL is already enabled, it will be done the first time the rate is changed while the PLL is disabled.
• dyn_ramp — Callback which can be used to define a custom dynamic ramp function for a given PLL.
• pre_rate_change — Callback which is invoked just before changing PLL's rate.
• post_rate_change — Callback which is invoked right after changing PLL's rate.

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🌈 Description 🌈

okay so the flags, let me walk you through them one by one, because each one is genuinely doing the most 🫶

• TEGRA_PLL_USE_LOCK — This flag indicated to use lock bits for PLL locking. If not set it will use lock_delay value to wait.
• TEGRA_PLL_HAS_CPCON — This flag indicates that CPCON value needs to be programmed to change output frequency of the PLL.
• TEGRA_PLL_SET_LFCON — This flag indicates that LFCON value needs to be programmed to change output frequency of the PLL.
• TEGRA_PLL_SET_DCCON — This flag indicates that DCCON value needs to be programmed to change output frequency of the PLL.
• TEGRA_PLLU — PLLU has inverted post divider. This flags indicated that it is PLLU and invert post divider value.
• TEGRA_PLLM — PLLM has additional override settings in PMC. This flag indicates that it is PLLM and use override settings.
• TEGRA_PLL_FIXED — We are not supposed to change output frequency of some plls.
• TEGRA_PLLE_CONFIGURE — Configure PLLE when enabling.
• TEGRA_PLL_LOCK_MISC — Lock bit is in the misc register instead of the base register.
• TEGRA_PLL_BYPASS — PLL has bypass bit
• TEGRA_PLL_HAS_LOCK_ENABLE — PLL has bit to enable lock monitoring
• TEGRA_MDIV_NEW — Switch to new method for calculating fixed mdiv it may be more accurate (especially if SDM present)
• TEGRA_PLLMB — PLLMB has should be treated similar to PLLM. This flag indicated that it is PLLMB.
• TEGRA_PLL_VCO_OUT — Used to indicate that the PLL has a VCO output

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🦋 SEE ALSO 🦋

• Kernel file ./drivers/clk/tegra/clk.h
• struct tegra_clk_sync_source(9)
• struct tegra_clk_frac_div(9)
• struct tegra_clk_pll_freq_table(9)
• struct pdiv_map(9)
• struct div_nmp(9)
• struct tegra_clk_pll(9)
• struct tegra_audio_clk_info(9)
• struct tegra_clk_pll_out(9)
• struct tegra_clk_periph_regs(9)
• struct tegra_clk_periph_gate(9)
• struct tegra_sdmmc_mux(9)

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💀 friendly reminder bestie: this page is from ./drivers/clk/tegra, dated October 2026, and its title is struct tegra_clk_pll_params(9) — screenshot it, cite it, cite it again, periodt 👑

that's the whole page, you ate it, i'm obsessed, go forth and clock 🌸🧚💜