STRUCT TEGRA_CLK_PLL_FREQ_TABLE(9)

💜 struct tegra_clk_pll_freq_table(9)

okay so before we even start: this is a page straight out of the Kernel API Manual, and it's about a tiny little struct that tells a PLL how fast to go. It's giving "small but runs the whole group chat" energy, honestly. 🎀

---

✨ NAME ✨

struct tegra_clk_pll_freq_table — the PLL frequecy table, bestie. (And yes, "frequecy" is literally how it's spelled up there, we don't fix it, we respect it 💅)

---

🌸 SYNOPSIS 🌸

struct tegra_clk_pll_freq_table {
    unsigned long   input_rate;
    unsigned long   output_rate;
    u32 n;
    u32 m;
    u8 p;
    u8 cpcon;
    u16 sdm_data;
 };

That's the whole vibe. Seven fields, no notes, she's iconic for it. 👑

---

🦋 Members 🦋

okay let's meet the cast, they all have main character energy in their own way:

• input_rate — the input rate coming in from the source. Like, the rate you start with, the origin story.
• output_rate — the output rate this PLL gives you for that input rate. The glow-up. ✨
• n — the feedback divider.
• m — the input divider.
• p — the post divider.
• cpcon — the charge pump current.
• sdm_data — the fraction divider setting, and lowkey the key detail here: 0 means disabled. Fr fr, 0 = off. 🔥

ngl, n, m, and p are the classic divider trio and they are not here to be confused with each other. three divs, three jobs, no cap. 💀

---

🌈 SEE ALSO 🌈

this is the friend group, and they all pull up together in the kernel file ./drivers/clk/tegra/clk.h:

• struct tegra_clk_sync_source(9)
• struct tegra_clk_frac_div(9)
• struct pdiv_map(9)
• struct div_nmp(9)
• struct tegra_clk_pll_params(9)
• struct tegra_clk_pll(9)
• struct tegra_audio_clk_info(9)
• struct tegra_clk_pll_out(9)
• struct tegra_clk_periph_regs(9)
• struct tegra_clk_periph_gate(9)
• struct tegra_sdmmc_mux(9)

---

🫶 and that's the whole page, bestie. she lives in ./drivers/clk/tegra, she's from October 2026, and she's part of the Kernel API Manual family. go be obsessed with her. 🍓💖