STRUCT TEGRA_CLK_PERIPH_GATE(9)

๐Ÿ“ฆ version 7.3.1, in nixpkgs unstable

โœจ okay bestie, welcome to the Kernel API Manual page for struct tegra..._periph_gate(9) โ€” the peripheral gate clock one. it's giving kernel-clock realness, and we're gonna cover every field, flag, and reference, no skips ๐Ÿ’…โœจ

๐Ÿ’– NAME ๐Ÿ’–

struct tegra_clk_periph_gate โ€” peripheral gate clock. periodt ๐Ÿ’–


โœจ SYNOPSIS โœจ

struct tegra_clk_periph_gate {
    u32 magic;
    struct clk_hw           hw;
    void __iomem            *clk_base;
    u8 flags;
    int clk_num;
    int *enable_refcnt;
    const struct tegra_clk_periph_regs *regs;
 };

๐Ÿ‘‘ Members ๐Ÿ‘‘

okay so here's the whole member lineup, bestie โ€” every single one, no cap:

  • magic โ€” magic number to validate type. it's the vibe check for the struct ๐Ÿ”ฎ
  • hw โ€” handle between common and hardware-specific interfaces. the little bridge between worlds ๐Ÿซถ
  • clk_base โ€” address of CAR controller. that's where the clock action lives ๐Ÿ“
  • flags โ€” hardware-specific flags. yes, the flag field is serving main character energy ๐Ÿšฉ
  • clk_num โ€” Clock number. the numeric ID moment ๐Ÿ”ข
  • enable_refcnt โ€” array to maintain reference count of the clock. keeping track, always tracking ๐Ÿ“Š
  • regs โ€” Registers to control the peripheral. the control panel, basically ๐ŸŽ›๏ธ

๐Ÿ’œ Description ๐Ÿ’œ

okay so check it โ€” the flags situation is this:

  • TEGRA_PERIPH_NO_RESET โ€” this flag indicates that reset is not allowed for this module. like, absolutely not, bestie ๐Ÿšซ
  • TEGRA_PERIPH_ON_APB โ€” if peripheral is in the APB bus then read the bus to flush the write operation in apb bus. this flag indicates that this peripheral is in apb bus. bus behavior, very demure ๐ŸšŒ
  • TEGRA_PERIPH_WAR_1005168 โ€” Apply workaround for Tegra114 MSENC bug. workaround era, my condolences to the bug ๐Ÿ˜ญ

๐Ÿฆ‹ SEE ALSO ๐Ÿฆ‹

kernel file: ./drivers/clk/tegra/clk.h โ€” and then the whole struct squad, in order:

  • struct tegra_clk_sync_source(9)
  • struct tegra_clk_frac_div(9)
  • struct tegra_clk_pll_freq_table(9)
  • struct pdiv_map(9)
  • struct div_nmp(9)
  • struct tegra_clk_pll_params(9)
  • struct tegra_clk_pll(9)
  • struct tegra_audio_clk_info(9)
  • struct tegra_clk_pll_out(9)
  • struct tegra_clk_periph_regs(9)
  • struct tegra_sdmmc_mux(9)

mwah ๐Ÿ’‹ โ€” footer tea: source/version ./drivers/clk/tegra, date October 2026, page struct tegra..._periph_gate(9). bye bestie ๐Ÿซถ

๐Ÿ“ฆ where this page comes from