STRUCT TEGRA_CLK_FRAC_DIV(9)

💅 struct tegra_clk_frac_div(9) 💅

okay so bestie, welcome to the Kernel API Manual 🫶 — today's main character is struct tegra_clk_frac_div, aka the fractional divider clock. she's a struct, she's iconic, and she's about to make ur clock tree make sense. periodt. ✨

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🌸 NAME 🌸

struct tegra_clk_frac_div — fractional divider clock 💖

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🎀 SYNOPSIS 🎀

struct tegra_clk_frac_div {
    struct clk_hw   hw;
    void __iomem    *reg;
    u8 flags;
    u8 shift;
    u8 width;
    u8 frac_width;
    spinlock_t *lock;
 };

like, that's the whole vibe right there. no cap. 👑

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🦋 Members 🦋

• hw — the handle between the common clock interfaces and the hardware-specific ones 🌈 the little bridge between two worlds, honestly kind of giving main character energy
• reg — the register containing the divider 📍 that's where she lives
• flags — hardware-specific flags 🚩 (scroll down, there's a whole section, it's a lot, i love it)
• shift — shift to the divider bit field ➡️ how far u gotta scoot over
• width — width of the divider bit field 📏 how many bits she's occupying
• frac_width — width of the fractional bit field 🍰 the fractional one!! separate width!! yes bestie
• lock — register lock 🔒 nobody touches the register without the lock, we respect boundaries here

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✨ Description ✨

okay so the Flags section, and bestie, listen up, there are FOUR of them and each one does something different 💅

• TEGRA_DIVIDER_ROUND_UP — this flag indicates to round up the divider value 🔥 round UP, not down, don't get it twisted
• TEGRA_DIVIDER_FIXED — fixed rate PLL dividers have an additional override bit, and this flag indicates that this divider is for a fixed rate PLL 📌 iykyk
• TEGRA_DIVIDER_INT — some modules cannot cope with the duty cycle when the fraction bit is set 😭 so this flag indicates to calculate a divider for which the fraction bit will be zero — yeah, we zero it out, it's the only way she'll behave
• TEGRA_DIVIDER_UART — the UART module divider has an additional enable bit which is set when the divider value is not 0 🎀 this flag indicates that the divider is for the UART module ⭐

ngl these flags are doing a LOT of emotional labor for one u8. respect. 🫶

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🔥 SEE ALSO 🔥

Kernel file ./drivers/clk/tegra/clk.h — go read her, she's the source of truth 💜

and the whole friend group:

• struct tegra_clk_sync_source(9)
• struct tegra_clk_pll_freq_table(9)
• struct pdiv_map(9)
• struct div_nmp(9)
• struct tegra_clk_pll_params(9)
• struct tegra_clk_pll(9)
• struct tegra_audio_clk_info(9)
• struct tegra_clk_pll_out(9)
• struct tegra_clk_periph_regs(9)
• struct tegra_clk_periph_gate(9)
• struct tegra_sdmmc_mux(9)

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🦋 okay that's the whole page bestie, u ate that 💅

sign-off time: this lil masterpiece lives in ./drivers/clk/tegra, dated October 2026, and yes she's still serving struct tegra_clk_frac_div(9) energy 🌸💖✨