STRUCT SUNXI_NFC(9)

πŸ“¦ version 7.3.1, in nixpkgs unstable

πŸ’– NAME πŸ’–

okay so bestie, welcome to the struct sunxi_nfc(9) page from the Kernel API Manual β€” and yes, this struct is literally where sunxi NAND controller information gets stored. no cap. 🫢

struct sunxi_nfc β€” stores sunxi NAND controller information.


✨ SYNOPSIS ✨

here's the whole struct, exactly as it appears β€” do not come for me about the semicolons, they're iconic πŸ’…

       struct sunxi_nfc {
           struct nand_controller controller;
           struct device *dev;
           void __iomem *regs;
           struct clk *ahb_clk;
           struct clk *mod_clk;
           struct clk *ecc_clk;
           struct clk *mbus_clk;
           struct reset_control *reset;
           unsigned long assigned_cs;
           unsigned long clk_rate;
           struct list_head chips;
           struct completion complete;
           struct dma_chan *dmac;
           bool use_mdma;
           struct sunxi_nfc_mdma_desc *mdma_desc;
           dma_addr_t mdma_desc_dma;
           const struct sunxi_nfc_caps *caps;
        };

πŸŽ€ Members πŸŽ€

every member gets its moment, bestie β€” none skipped, fr fr:

  • controller β€” the base controller structure, the whole foundation vibe.
  • dev β€” the parent device, and yep, it's used to print error messages.
  • regs β€” the NAND controller registers.
  • ahb_clk β€” the NAND controller AHB clock.
  • mod_clk β€” the NAND controller mod clock.
  • ecc_clk β€” the NAND controller ECC clock.
  • mbus_clk β€” the NAND controller MBUS clock.
  • reset β€” the NAND controller reset line.
  • assigned_cs β€” bitmask describing already assigned CS lines.
  • clk_rate β€” the NAND controller current clock rate.
  • chips β€” a list containing all the NAND chips attached to this NAND controller.
  • complete β€” a completion object used to wait for NAND controller events.
  • dmac β€” the DMA channel attached to the NAND controller.
  • use_mdma β€” use an internal MBUS DMA backend.
  • mdma_desc β€” H6-style MBUS DMA descriptor.
  • mdma_desc_dma β€” DMA address of mdma_desc.
  • caps β€” NAND Controller capabilities.

πŸ‘€ SEE ALSO πŸ‘€

you want the lore? start with the kernel file ./drivers/mtd/nand/raw/sunxi_nand.c, then peek at struct sunxi_nand_chip_sel(9), struct sunxi_nand_hw_ecc(9), and struct sunxi_nand_chip(9). iykyk πŸ’œ


and that's the whole page, bestie! this cutie came from the ./drivers/mtd/nand/raw source/version line and is dated October 2026, so you know exactly where the lore is from. mwah πŸ’‹βœ¨

πŸ“¦ where this page comes from